The SivaKali Tech SMBUS Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with SMBUS version 3.3.1 specification.
Full SMBus Controller Functionality.
Two wire serial interface from 100 KHz to 1 MHz with the following Data rates
supported:
--> Standard mode
--> Fast mode
--> Fast mode plus
Supports command code Protocols
--> Write Byte/Word
--> Read Byte/Word
--> Process Call
--> Block Write/Read
--> Block Write-Block Read Process Call
--> Write 32 Protocol
--> Read 32 Protocol
--> Write 64 Protocol
--> Read 64 Protocol
Supports Non command code Protocols
--> Quick Command Protocol
--> Send Byte Protocol
--> Receive Byte Protocol
Supports I2C Write/Read command
Supports Address Resolution Protocol
Supports SMB Alert signal and SMB Suspend signal
Supports Packet Error Checking
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module inter connects all the sub modules in SMBus controller ( CSR, prescaler, MFSM and SFSM). Ports of core module are the top level ports of Controller IP.
PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for I3C.
MASTER FSM: Master FSM module process the commands once pending request from CSR and host controller bus is enabled.For write transfer master FSM will send slave address, R/W bit,Write data and waits for ACK/NACK from slave.
SLAVE FSM: SFSM module process SMBus Slave commands once start is detected. SFSM responds to SMBus Slave commands ACK/NACK for Write transfer and Read data for read transfer
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 28nm
41.99K
25MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD virtula ultrascale
51685 LUT's
25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
