The SivaKali Tech TS5 Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with JEDEC TS5111, TS5110 specifications.
Full TS5 Slave Controller functionality.
Supports two wire bus serial interface
Supports all the TS5 commands as per the specs
I2C with maximum speed up to 1 MHz
I3C with maximum speed up to 12.5 MHz
Supports two unique device addresses selected by SA pin.
Supports start, repeat start and stop for all possible transfers.
Supports START byte generation and handling.
Supports bus reset.
Supports in-band interrupts.
Supports parity error check.
Supports packet error check.
Supports device read address pointer mode.
Supports all error handling as per specs
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the TS5 Slave Controller IP. Ports of core module are the top level ports for the SDRAM IP.
FSM: This converts analog thermal signals into digital data using an internal ADC. TS5 Slave Controller IP stores user-defined thresholds in its internal registers. Both power and data are managed over a simple two-wire interface. The TS5 Slave Controller IP can alert the Master of a Thermal emergency using the existing data lines.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
TSMC 28nm
20.45K
10MHz
UMSC 55nm
46.52K
10MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
187.25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
