CORE: Core module interconnects all the sub-modules in the Peripheral IP. Ports of core module are the top level ports for the Peripheral IP.The Core Module acts as the central interconnect hub that integrates and coordinates all the sub-modules within the SoundWire I3S Peripheral IP.
CSR: The Control and Status Register(CSR) Module maintains all the configuration and monitoring registers used by the Peripheral IP. It controls operational parameters, interrupt settings, DMA interface control, CDC and FIFO’s for store audio samples to and from peripheral.
US TIMER: The Microsecond Timer (US Timer) module generates the us tick pulse every microsecond width used for microsecond-resolution timing operations within the Peripheral IP.
PL SM: The Peripheral Link State Machine (PL_SM) module implements the state control logic for the SoundWire Peripheral Link layer. It follows the MIPI SoundWire specification, governing link bring-up, configuration, and runtime management.
PBR SM: The Peripheral Bus Reset State Machine (PBR_SM) provides straightforward monitoring of the two SWI3S bus lines (DP and DN) to ensure that the Peripheral recognizes a Bus Reset sequence regardless of its current state.
PLC SM: Peripheral Link Control Request State Machine (PLC_SM) monitors the DP/DN lines to detect when the Bus Master issues a Link Control Request to the Peripheral.
CDS: The Control Data Stream (CDS) Module manages the bidirectional transfer of control and status information between the Peripheral and Peripheral devices. This block implements 8b/10b encoder, 10b/8b decoder, serializer and deserializer.
CTP: The Command Transport Protocol (CTP) Module is responsible for executing andmanaging the SoundWire I3S command sequences between the Peripheral and Peripheral devices.
PTL: The Payload Transport Layer (PTL) Module handles streaming data payloads such as audio samples. It provides a structured channelized architecture for multiple datastreams and integrates DPort submodules for each channel.
DPORT: The Data Port (DPort) Module manages the source and sink logic for data streams.Each DPort operates as a programmable state machine that controls sample flow based on channel configuration.
SCRAMBLER: The Scrambler Module performs data scrambling and descrambling functions to minimize DC bias and EMI on the transmission line. This ensures balanced data patterns and compliant signal characteristics on the SoundWire I3S physical interface.
MAPPER: The Mapper Module performs mapping of audio sample data and control bits between logical data channels and the PHY interface. It defines how samples are serialized and transmitted over the link.
PHY IF: The Physical Interface (PHY_IF) Module drives and samples data at the physical layer according to the SoundWire I3S protocol. It is responsible for electrical-level interfacing and NRZ encoding/decoding.
