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SDIO Host Controller IIP

Secure Digital Input Output Host Controller IIP

SDIO Host Controller IIP

Overview

It supports two types of data transmission mode:

1)SD mode

2)SPI mode

COMPETITIVE ADVANTAGE

The SivaKali Tech SDIO Host Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with SD Host Controller Specification version 6.0
  • Compliant with SDIO Physical Specification version 4.20
  • Compliant with Part E1 SDIO specification 4.10
  • Supports SDMA, ADMA2 and ADMA3 modes
  • Supports 1-bit, 4-bit SD bus mode and SPI Bus mode
  • Supports SDR12, SDR25 ,DDR50, SDR 50 and SDR104 speeds
  • Supports Single byte, Single block, Multi –block(finite and infinite) transfers
  • Supports suspend and resume
  • Supports read wait
  • Supports card detection
  • Fully synthesizable
  • Static synchronous design
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the SDIO Host Controller IIP. Ports of core module are the top level ports for the SDIO Host Controller IIP

GENCLK: This module has MMC clock generator logic. The clock divider value is loaded from the register CLOCK_TIMEOUT_CONTROL. This value is from the MMC clock frequency select (either via driver programmed or selected preset value)

CDET: Card Detect State Machine is either the External i_sdif_cd_n or the Internal Signal (Card Detect Test Level) is muxed for Card Detect Logic. The selection is based on the Card Detect Signal Select.

CSR: This module includes all the registers like block size, block count, address,argument ...etc and also it includes card interrupt logic. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. The registers can get its data from both the internal and external system interface. Likewise, it can be retrieved by both the internal and external system interface.

CTRL: This module consist of Command generation,Data transmission and Data recieve, Response check, tuning operations

TIMEOUT: For data timeout, when the TXD control or RXD control enables the counting of timeout value, the counter start counting. When the counting is disabled, the counts are reset to zero.

DMA: This module suports three types of DMA. SDMA (Single Operation DMA) performs a read / write SD command operation. ADMA2 performs a read / write SD command operation at a time. ADMA3 can program multiple read / write SD commands operation in a Descriptor Table. ADMA3 is suitable to perform very large data transfer.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem clock frequencyCrystal clock frequencySDIO clock frequency
TSMC 28nm39.20K100MHz200Mhz200Mhz
TSMC 180nm59.35K100MHz200Mhz200Mhz
TSMC 130nm55.52K100MHz200Mhz200Mhz
TSMC 90nm55.52K100MHz200Mhz200Mhz
TSMC 12nm60.28K100MHz200Mhz200Mhz
UMSC 55nm68.45K100MHz200Mhz200Mhz
SMIC 40nm40.70K100MHz200Mhz200Mhz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.