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NAND CTRL IP

NAND Controller IIP

NAND CTRL IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech NAND CTRL IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Optimized for high-performance computing, storage appliances, and mobile SoCs. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Maximum Bandwidth: Intelligent controller architecture maximizes bus utilization and minimizes latency.

Data Integrity: Advanced ECC (Error Correction Code) and reliability features for enterprise-grade data protection.

Broad Compatibility: Supports a wide range of JEDEC standard memory devices from major vendors.

PHY Independent: DFI-compliant interface allows easy integration with third-party or foundry-provided PHYs.

FEATURES
  • Implemented in Unencrypted Verilog, VHDL and SystemC.
  • Supports NAND protocol standard draft specifications.
  • Supports 8-bit and 16-bit flash devices.
  • Supports page size from 0.5 KB onwards.
  • Supports only single chip select.
  • Supports MLC and SLC.
    • MLC - Multi level cell
    • SLC - Single level cell
  • Supports programmable NAND flash timing parameters.
  • Supports up to 4 NAND devices.
  • Supports wear leveling with 516-byte mode.
  • Supports dedicated NAND flash interface with hardware controlled read and write accesses.
  • Supports software controlled command and address transfers to support wide range of flash devices.
  • Supports write and read cycles operations.
  • Compatible with industry standards like ONFI for high-speed operations.
  • Supports Address translation.
  • Supports Command sequencing.
  • Supports DMA interface.
  • Supports programmable clock frequency of operation.
  • Supports ECC for MLC NAND Flash:
    • Supports Reed-Solomon error correction encoding and decoding.
    • Uses Reed-Solomon code words with 9-bit symbols over GF (2 9), a total codeword length of 469 symbols including 10 parity symbols, and giving a minimum Hamming distance of 11.
    • Corrects up to 8 symbol errors per codeword.
    • Error Correcttion can be turned on and off to match the requirements of the application.
    • Parity generator for error correction encoding.
    • Wear leveling information can be integrated into protected data.
    • Interrupts generated after completion of error correction task with three interrupt registers.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the NAND Controller IP. Ports of core module are the top level ports for the NAND Controller IP.

FSM: NAND Controller IP FSM generates and controls critical NAND interface signals to ensure operations occur in the correct order and timing. It also waits for internal NAND operations to complete, coordinates with ECC logic for error detection and correction.

ECC: ECC module is responsible for detecting and correcting data errors. Also ecc block generates redundant parity or check bits for data safety.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock Frequency
TSMC 28nm21K50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.