The SivaKali Tech JTAG Slave To APB Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Forming the high-speed communication backbone of complex System-on-Chips. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Deadlock Free: Robust routing logic prevents system hang-ups under heavy load conditions.
Low Latency Bridging: Efficient clock domain crossing and protocol conversion with minimal cycle overhead.
High Frequency: Pipelined architecture designed to close timing at high clock frequencies in modern nodes.
Scalable: Easily configurable for simple bus fabrics or complex, multi-layer network-on-chip (NoC) implementations.
FEATURES
Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6
Supports all the JTAG tap instructions.
Supports programmable clock frequency of operation.
Supports Instruction register and data register of various sizes.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.
Supports APB Master Read/ Write capability.
Supports APB Slave.
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the JTAG Slave To SoC Bridge IIP. Ports of core module are the top level ports for the JTAG Slave To SoC Bridge IIP.
CSR: CSR Module has all the configuration registers. The contents of configuration registers are decoded and assigned to its respective output ports based on its functionality.
FSM: FSM module generates the JTAG transactions on based on commands from CSR block. This blocks implements the features of JTAG spec.
TAP: TAP module generates the JTAG transactions on based on tap state movements.This blocks implements the features of JTAG spec.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Clock Frequency
TSMC 12nm
10.57K
100MHz
TSMC 28nm
7.08K
100MHz
TSMC 90nm
10.11K
100MHz
TSMC 130nm
10.11K
100MHz
TSMC 180nm
10.67K
100MHz
UMSC 55nm
12.70K
100MHz
SMIC 40nm
7.44K
100MHz
GF 180nm
7.71K
100MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
988 LUT's
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
