MIPI APHY IIP

• Supports MIPI A-PHY specification v1.0, v1.1 and v2.0.
• Supports single lane and dual lane, point-to-point and serial communication
• technology.
• Supports PHY layer and Data link layer features.
• MIPI A-PHY provides a main unidirectional data stream and a bi-directional low-
• throughput command and control data stream, and can optionally also deliver the
• required power supply to peripheral units (i.e., the sensors and/or displays at the
• edge of the network) directly via the A-PHY data line.
• The model has a rich set of configuration parameters to control MIPI A-PHY
• functionality.
• Support APPI interface between MIPI A-PHY and Native protocol.
• Support multiple speed gears ranging from 2Gbps up to 32Gbps.
• Support 7 discrete Downlink Gears: G1, G2, G3, G4, G5, G6, G7 and Uplink shall
• be 100Mbps at U1 gear, 200Mbps at U2 gear and 1600Mbps at U3 gear.
• Support two types of profiles:
• -->Profile 1 (P1-NRZ 8B/10B)
• -->Profile 2 (P2 -PAM 4, 8 ,16)
• Support clock recovery, Sink Transmitter shall use the recovered Source clock to
• generate the proper Sink transmit clock, to reach the proper port rate.
• Support Re transmission request / ACK types.
• Support Scrambler as per specs.
• Support Re-Training sequence.
• Support Repetitive Scrambler Reset Test mode(RSRT).
• Support two types of Startup Procedure:
• -->Mission Mode startup
• -->Unidirectional startup
• Support Wake-Up protocol and below Mode of operation:
• -->Non active Mode
• -->Active Mode
• Implements below PHY layer architecture:
• -->MIPI A-PHY P1 G1/G2 Architecture
• -->RTS By-Pass
• -->8B/10B PCS
• -->PMD
• -->MIPI A-PHY P2 G1/G2 Architecture
• -->RTS for Uplink and Downlink
• -->8B/10B PCS
• -->PMD
• -->MIPI A-PHY G3-G7 Architecture
• -->RTS for Uplink and Downlink
• -->8B/10B PCS for Uplink
• -->PAM 4, 8 ,16 PCS for Downlink
• -->PMD
• Support below Data Link feature:
• -->Link service
• -->Local function
• -->Multi-port function
• -->Network function
• Supports Test Pattern and ACMD/ACMP registers.
• Supports Back to Back to A-Packet transmission.
• Supports continuous Packet start with respect to the APPI request.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

CORE: Core module interconnects all the sub-modules in the MIPI_APHY IP. Ports of core module are the top level ports for the MIPI_APHY IP.

APPI TX: Appi tx module collects the A-packet from NAPAL (APPI interface) via appi signals based on appi widths(16/32/64).

RTS TX: Rts tx module will update the values to PHY fields (message counter, sub-constellation type, tx delay and original indication) to each A-packets. If RTS is disabled, Data is bypassed to the BSC TX module. If RTS enabled, A-packets received from appi tx stores in the buffer for retransmission. When an RTS request is received, then requested MC packet will be retransmitted from the buffer. Rts tx transmits the data to BSC TX for processing it.

BSC TX: In this module A-packet will get added with packet start and packet end indications and caluclation of crc.

SCR TX: Scrambler module is used to scramble the valid A-packet data bytes.

ENCODER: Encoder performs 8B/10B encoding for received scrambled data.

GEARBOX TX: Gearbox is used to convert the 80-bit encoded data into 20/40/80 bit based on the configured PMD width. It will drive the data in the PMD signals which is connected with the other APHY device.

GEARBOX RX: Gearbox rx module will to the concatenation of received PMD width of bits(20/40/80) in to 80 bits.

CDET RX: This module used to dectect the comma characters and locks the position.

DECODER: Decoder module is used to do 10b/8b decoding process.

SCR RX: Scrambler rx module is used to descramble the decoded data.

BSC RX: Bsc rx module is used to remove the control character and checks the CRC.

RTS RX: Rts rx module is used to store the A-packets in a buffer up to max rts delay.

APPI RX: Appi rx module sends the A-packets to NPAL based on APPI widths(16/32/64) via appi signals.

LSS: Lss module is used for linkup procees and control communication between tx and rx of SINK and SOURCE.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.