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MIPI I3C Master IIP

MIPI Improved Inter-Intergrated Circuit Master IIP

MIPI I3C Master IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI I3C Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • Compliant with MIPI I3C version 1.2 specifications.
  • Compliant with JEDEC Module Sideband Bus version 1.0 specification.
  • Full MIPI I3C Master Functionality.
  • Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported:
    • Standard speed Supports all topologies
    • Single Master – Multi Slave
    • Single Master – Single Slave
    • Multi Master – Multi Slave
    • Multi Master – Single Slave
  • Legacy I2C Device co-existence on the same Bus instance
  • Dynamic Addressing while supporting Static Addressing for legacy I2C devices.
  • Supports I3C address arbitration.
  • Supports Single Data Rate (SDR) messaging.
    • SDR with Direct CCC
    • SDR with Broadcast CCC
  • Supports High Data Rate (HDR) messaging
    • HDR-Dual Data Rate Mode (HDR-DDR)
    • HDR-Ternary symbol for Pure bus (HDR-TSP)
    • HDR-Ternary symbol Legacy inclusive bus (HDR-TSL)
    • HDR with Direct CCC
    • HDR with Broadcast CCC
  • In-Band Interrupt support and Hot-Join support
  • Support for all I3C Common Command Codes(CCCs)
  • Auto-Reject for In-Band Interrupt and Hot-Join (NACK and directed DISEC CCC to disable)
  • Supports interrupt masking
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Master IP. Ports of core module are the top level ports for the Master IP. SCL clock is derived from i_clk based on prescaler value.

GLITCH FILTER: Glitch filter is used to remove the spikes shorted than 50 ns in duration for Legacy I2C mode.

PRESCALER: Prescalermodule is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for I3C.

FSM: FSM module process the commands once pending request from CSR and host controller bus is enabled

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 28nm29.38K500MHz
UMSC 55nm75.65K500MHz
SMIC 40nm35.17K500MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD virtula ultrascale51685 LUT's48MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.