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LPC Device AHB Bridge IIP

low-pin-count Bus Interface Device AHB Bridge IIP

LPC Device AHB Bridge IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech LPC Device AHB Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Forming the high-speed communication backbone of complex System-on-Chips. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Deadlock Free: Robust routing logic prevents system hang-ups under heavy load conditions.

Low Latency Bridging: Efficient clock domain crossing and protocol conversion with minimal cycle overhead.

High Frequency: Pipelined architecture designed to close timing at high clock frequencies in modern nodes.

Scalable: Easily configurable for simple bus fabrics or complex, multi-layer network-on-chip (NoC) implementations.

FEATURES
  • Compliant with version 1.1 LPC Specification
  • Full LPC Device AHB Bridge functionality
  • Supports the following operations
    • Memory read and write
    • I/O read and write
    • DMA read and write
    • Bus Master memory read and write
    • Bus Master I/O read and write
    • Firmware memory read and write
    • TPM read and write
  • Supports all transfer sizes
  • Supports 128 Bytes for Firmware read
  • Support a variable number of wait-states
  • Supports Sync timeout detection and abort transfer
  • Supports Sync field based error detection and reporting
  • Supports wake-up and other power state transitions
  • Peripheral is capable of responding to all types of LPC transactions
  • Supports Abort Mechanism as per specification
  • Supports soft reset
  • Supports Reset policy
  • Supports AHB Master Read/Write capability
  • Supports AHB Slave
  • Supports LPME#, LPCPD#, CLKRUN# Power management signals
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the LPC Device Soc bridge IP. Ports of core module are the top level ports for the LPC Device Soc bridge IP.

FSM: FSM module receives the transactions from the LPC Bus and process the serial data. This blocks implements all the features of LPC specs. Transmission occurs independently any action of the Device module.

LDRQ: This module controls the LDRQ# lines to handle the DMA channel and Bus Mastering, which will be requested from LPC devices. LDRQ# is synchronous with LCLK.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

BRIDGE: The Module BRIDGE is used to process bridge commands from/to LPC Host. This module is interacts with AHB Master.

AHB Slave: The AHB Slave as external interface helps to write or read control and status register in CSR module. The SoC Slave ports connect CSR and AHB Slave Module.

AHB Master: The AHB Master as external interface helps to write data into descriptor memory or read data from descriptor memory. The SoC Master ports connect Bridge and AHB Master Module.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyProtocol Clock Frequency
TSMC 28nm14.06K100MHz33MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e23435 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.