MIPI SOUNDWIRE SLAVE IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI SOUNDWIRE SLAVE IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES

Compliant with MIPI SOUNDWIRE version 1.1x Specification.
Full MIPI SOUNDWIRE Slave functionality
Supports slave-to-slave transport.
Supports up to 8 data lanes.
Supports modified-NRZI data encoding.
Special internal register for each devices.
Supports configurable data width of 8,16 and 32.
Supports configurable PDI count, type, command FIFO depth, data lane count, data port memories.
Supports clearly de-marked clock domains.
Supports extensive clock gating.
Provides bi-directional DATA line and unidirectional CLK line.
Enumeration for device is supported.
Provides Arbitration mechanism to access the port.
Provides limited retransmission of Messages.
Supports Frame layer to interleave Control space and data space in a Subframe.
Supports all Core Message types.
User Defined protocol is supported.
Supports Flow control mechanism.
Supports Collision Detection for Message channel as well as for Data channel.
Supports various Error Management mechanisms.

Error on Segments.
Framing error.
Parity error.
Messaging error.
Error on Synchronization.
CRC error.

Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

SLAVE: The Slave module defines that the Slave Device which responds to the control information on a SoundWire bus.

SOURCE DATA PORT: The source data port module defines that Data Port which takes Payload sample data from the external (audio) interface and produces data to be transported via the SoundWire bus.

SINK DATA PORT: The sink data port module defines that Data Port which consumes data that has been transported on the SoundWire bus and delivers it as Payload sample data to the external (audio) interface.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	50.11K	100MHz
UMSC 55nm	75.12K	100MHz
SMIC 40nm	45.73K	100MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	16525 LUT's	100MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.