IEC7816 Master IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech IEC7816 Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Compliant with ISO/IEC 7816-3 Specification.
Full IEC7816-3 Master functionality.
Supports all functions for complete smart card sessions,including
->Card activation and deactivation
->Cold/warm reset
->Answer to Reset (ATR) response reception
->Data transfers to and from the card
Supports adjustable clock rate and bit (baud) rate.
Supports configurable automatic byte repetition.
Supports commonly used communication protocols
->T = 0 for asynchronous half-duplex character transmission, and
->T = 1 for asynchronous half-duplex block transmission
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the IEC7816 Master IP. Ports of core module are the top level ports for the IEC7816 Master IP.

FSM: FSM module generates the IEC7816 transactions on Master based on commands from CSR block. This blocks implements all the features of IEC7816 spec.

RX-PRESCALER: RX Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial transmission clock input for IEC7816 Master.

TX-PRESCALER: TX Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial sampling clock input for IEC7816 Master.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for IEC7816 Master.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency
TSMC 28nm	7.01K	20MHz

FPGA Device and Family	Logic Resources	Clock Frequency
AMD-xcvu9p-flga2104-2L-e	11684 LUT's	20MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.