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ETHERNET 10G XAUI PCS IIP

ETHERNET 10G XAUI PCS IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 10G XAUI PCS IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES
  • Supports IEEE Standard 802.3.2022 Clause 48 for XAUI PCS
  • Supports 8b/10b encoding on each lane to generate code groups in transmit path
  • Supports 10b/8b decoding on each lane to convert received code groups to 32 XGMII data bits and 4 XGMII control bits
  • Supports synchronization of code groups on each lane to determine code group boundaries
  • Supports deskew of received code-groups from all lanes to an alignment pattern
  • Supports conversion of XGMII Idle control characters to (from) a randomized sequence of code-groups to enable serial lane synchronization, clock rate compensation and lane-to-lane alignment
  • Supports Loopback Functionality
  • Support link fault and error indications
  • Supports IEEE Standard 802.3az Energy Efficient Ethernet
  • Supports Configurable Management Interface (MDIO(Clause 45) / SoC Bus)
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Ethernet 10G XAUI PCS IP. Ports of core module are the top level ports for the Ethernet 10G PCS XAUI IP.

TX FSM: TX FSM module is used to implement both encapsulation and 8B/10B encoding and transmitting to 4 lane.

PCS IDLE RANDOMIZER: This block is used to replacing the constant idle character with a pseudo-random sequence of code group, which is prevents the repetitive pattern on transmission line.

ENC8_8B_10B: To attain DC balance and for clock recovery,ENC8_8B_10B module is used for encoding the eight bit data into more transition ten bit code groups.

SYNC FSM: SYNC FSM module is used to synchronize the 10bit block from the incoming code group based on the Comma Detect.

COMMA DETECT: COMMA DETECT module is used to detect the valid code group on the receive PCS for acquiring alignment with the byte boundary.

DEC8_8B_10B:

DEC 8B/10B module is used for decoding the ten bit code groups into eight bit data once synchronization lock is attained. DESKEW FSM: This block process checks for the deskew character in all the lanes, only if synchronization is achieved in all the lanes.

CSR: CSR module has Control Status registers that controls the IP all the registers. The contents of the registers are decoded and assigned to its respective output port based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencyTX Clock FrequencyRX Clock Frequency
TSMC 28nm150.72K167.7MHz156.25MHz156.25MHz
UMSC 55nm177.72k167.7MHz156.25MHz156.25MHz
SMIC 40nm162.72k167.7MHz156.25MHz156.25MHz

FPGA Device and FamilyLogic ResourcesClock FrequencyTX Clock FrequencyRX Clock Frequency
AMD-xcvu9p-flga2104-2L-e25127 LUT's167.7MHz156.25MHz156.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.