ETHERNET 10G MAC IIP

• Compliant with IEEE Standard 802.3-2022 specification of clause 46
• Supports full duplex mode of operation
• Supports Standard 10Gbps Ethernet link layer data
• Supports XGMII interface operating at 156.25MHz
• Supports Programmable Inter Packet Gap(IPG) and Preamble length
• Supports MDIO Clause 45 Interface
• Supports start control character alignment
• Supports statistics counter to indicate the number of valid frame, error occurrence, etc ,.
• Supports Jumbo Frame
• Supports Loopback functionality
• Supports transmit and receive FIFO interface
• Supports FCS(CRC) transmission and reception
• Supports Pause frame-based flow control
• Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
• Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
• Optional Wake-on-LAN support
• Supports AXI stream Interface for System Interface In house UNH compliance tested
• Optional support for TCP/IP offload
• Optional support for IEEE Standard 1588-2008 PTP
• Optional support for DMA on both transmit and receive side
• Optional support for the following HiGig features
• HiGig
• HiGig+
• HiGig2
• HiGigLite
• 2.5G HiGig
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the ETHERNET 10G MAC IP. Ports of core module are the top level ports for the ETHERNET 10G MAC IP. TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.

TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC XGMII Interface by encapsulating the Ethernet packet and frame headers.

FLOW CTRL: Initiating the Transmission of pause frame-based on the Receive FIFO's threshold or External requests.

PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

LINK FAULT FSM: LINK FAULT FSM module detects the fault status from the received data and indicates status to the Transmitter.

RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.

RX CTRL : Receive Control block processes the data from MAC XGMII interface and push the data into RX ASYNC FIFO

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.