The SivaKali Tech LPSDR IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Supports LPSDR memory devices from all leading vendors
Supports 100% of LPSDR protocol standard LPSDR specification
Supports all the LPSDR commands as per the LPSDR specification
Supports following device density
512MB
1GB
Supports following device modes.
X16 Mode
X32 Mode
Supports programmable burst lengths: 1, 2, 4, 8, and continuous
Supports following burst type,
Sequential
Interleaved
Supports deep power down mode
Supports Auto-Refresh and Self-Refresh mode
Supports programmable partial array self refresh
Supports burst termination operation
Supports clock suspend operation
Supports all data rates as per specification
Supports programmable clock frequency of operation
Supports power down features
Fully synthesizable
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the LPSDR IP. Ports of core module are the top level ports for the LPSDR IP.
FSM: Controls LPSDR memory operations initialization, read/write sequencing and timing management. Interfaces with CSR to receive configuration and execute memory access commands.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
TSMC 28nm
32.56K
133MHz
UMSC 55nm
66.28K
133MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
187.25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
