The SivaKali Tech SHA IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Essential for safeguarding sensitive data in government, financial, and IoT applications. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Side-Channel Resistance: Design hardened against DPA (Differential Power Analysis) and other side-channel attacks.
High Performance: High-throughput encryption/decryption engines to match line-rate speeds of modern interfaces.
Standard Compliance: Fully compliant with NIST and ISO security standards.
Easy Integration: Standard system bus interfaces for straightforward integration into secure enclaves.
FEATURES
Fully compliant with the FIPS 180-2 specification and ensures standard-adherent operation across all supported configurations.
Accommodates input message lengths in multiples of 8 bits and 32 bits words.
Supports a maximum message length of 2^16 - 1 bits.
Dynamically programmable to support SHA1, SHA256, SHA384 and SHA512 modes.
Features automatic internal bit padding functionality.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION
CSR: Contains all configuration registers used to monitor status and control the RTL functionality.
SHA ROUNDS: Implements the core cryptographic round functions for the selected SHA Mode.
SHA PADDER: Manages the automatic bit padding process for the incoming message to meet FIPS standards.
HASH COMPUTATION: Calculates and outputs the final message digest (hash value) for given input data.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
SHA Clock Frequency
TSMC 28nm
43.64K
40MHz
40MHz
SMIC 40nm
45.89K
40MHz
40MHz
UMC 55nm
77.18K
40MHz
40MHz
FPGA Device and Family
Logic Resources
System Clock Frequency
SHA Clock Frequency
AMD-xcvu9p-flga2104-2L-e
7650 LUT's
40MHz
40MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
