DMA Controller with AHB IIP

• Supports 1-16 channel DMA Transmit and DMA Receive Engine
• Compliant with ARM AMBA 2 AHB Specification
• Optional support for AMBA 3 AHB-Lite and AMBA 5 AHB Specification
• Supports access for Ring and Chained Descriptor Structures
• Configurable Transmit and Receive Engine based on Host Memory Data Width
• Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian)
• Supports configurable DMA Transmit and DMA Receive FIFO based on Host Memory Data width
• Supports hardware DMA Control registers that can be written and read by CPU
• Round Robin algorithm for arbitration between DMA Transmit and Receive Engine to access SoC Master Bus
• SoC Master bus can be AXI/AHB/APB/OCP/Tilelink/Wishbone
• Supports AHB Slave bus
• Uses SoC Slave Interface to get Receive and Transmit descriptors and transfer the data to/from the system memory from/to FIFO inside the DMA controller
• User logic to map data fetched from Host to IP core or from IP core to host
• Supports following DMA transfers
• Memory to Memory
• Memory to Peripheral
• Peripheral to Memory
• Peripheral to Peripheral
• Supports Sideband DMA request and Grant based triggering of transfers as on option for peripherals
• Supports Scatter Gathers list
• Supports 8/16/32/64/128/256 bit wide data transfers
• Supports QoS per channel if SoC master interface supports Qos.
• Supports programmable burst capability per SoC master
• Supports both single data and burst data transfers, with burst size based on the burst length field in the DMA control registers
• DMA supports full duplex operation, processing read and write transfers at the same time
• Supports Link list based processor for autonomous operation
• Interface widths can be controller for each SoC master interface
• Supports different algorithms for selecting which channel to process and how long to process.
• Generate full 32-bit addresses on the SoC master interface
• Supports per Channel Interrupt output
• Supports up to 64 MB transfer per Buffer Descriptor (BD)
• Interrupts CPU on completion of a DMA transfer or an error
• Fully synthesizable
• Static synchronous design

CORE: Core module interconnects all the sub-modules in the DMA controller with AHB IIP. Ports of core module are the top level ports for the DMA controller with AHB IIP.

AHB SLAVE: AHB Slave is used to respond to a read or write operation within a given address-space range. It accepts address and control from the master and returns data/response.

AHB MASTER: AHB Master is use to initiate read and write operations by providing an address and control information.

DMA Arbiter: The arbiter looks for any write/read request and grants the bus to DMA Transmit or DMA Receive engine.

DMA FSM: This module implements DMA source state machine. It controls the fsms such as own bit check read local data, write data fetch

Router: This module implements DMA hardware router at top level.

Peripheral: It represents the destination devices that generate or consumes data from DMA transfers.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.