CORE: Core module interconnects all the sub-modules in the PSI5 Controller IP. Ports of core module are the top level ports for the PSI5 Controller IP.
TFSM: Tfsm module implements the PSI5 transmit state machine for timing sync generation and driving frame from ECU to sensor. In this module FSM transmits start pattern,sensor address, Frame control bit, configuration bit ,data and command information and stuff bits and calculates the CRC for 3-bit and 6-bit based on the type of enhance protocol and wait for the response. It performs the transactions on controller based on commands from CSR block.
RFSM: This module implements the PSI5 receiver state machine. In this module the RFSM samples the start bits, message bits, data and crc and stores the sampled data. It samples the data, timestamp and CRC and stores.
RPRESCALER: RPrescaler module implements receiver prescaler. RPrescaler module is used to divide the PSI5 clock based on the given rprescaler value to derive the serial clock input for the reception of PSI5 controller.
TPRESCALER: TPrescaler module implements transmit prescaler. TPrescaler module is used to divide the PSI5 clock based on the given tprescaler value to derive the serial clock input for the transmission of PSI5 controller. By using the divied cloclk the TFSM drives the frame from ECU to Sensor.
DECODER: Decoder module implements the manchester decoder. In this module we are decoding the start bit pattern and received data and FSM waits for bus to be free.
SYNC_ARB: Sync_arb module is responsible for managing and synchronizing multiple inputs from sensors that communicate over the PSI5. This module resolve the issue when multiple sensors transmit data simultaneously, the sync arbiter decides which channel needs to processed first based on the request.
TIMESTAMP: Timestamp module implements timestamp timer and clock divider. It is used to generate the clock by dividing the PSI5 clock based on the given Timestamp prescaler value and generates the timestamp data and external timestamp data.
J2176: J2716 module implements J2716 message bits processor for all slots. It will create the instance for each slot. It Implements the PSI5 receive J2726 message decoder.
J2176_SLOT: J2716_slot module implements J2716 message bits processor for given slot. It Implements the PSI5 receive J2726 message decoder for sampling the Enhanced Serial Message according to SENT SAE J2716 JAM 2010. It ensures the implementation of the SENT protocol within a PSI5 controller
CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.
