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CAN XL Controller IIP

Controller Area Network Extended Length IIP

CAN XL Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech CAN XL Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Supports CAN 2.0 A/B ISO11898 compliant
  • Supports CAN FD 1.1 compliant
  • Supports CAN XL 610_1v00000300.pdf(CiA 610-1) compliant
  • Full CAN transmit and receive functionality
  • Optimized for SAEJ1939 and AutoSAR
  • Supports bit rate up to 1 Mbps for classic CAN
  • Supports bit rate up to 5 Mbps for CAN FD
  • Supports CAN XL with flexible data rate(1 to 2048bytes)
  • Supports all types of frames
    • Data frame
    • Remote frame
    • Error frame
    • Overload frame
  • Supports 11 bit Identifier as well as 29 bit Identifier
  • Supports automatic response for remote frame
  • Supports all types of error detection
    • Bit error
    • Stuff error
    • CRC error
    • Form error
    • Acknowledgement error
    • Supports PCRC error and FCRC error in CAN XL
  • Supports Interrupt for each CAN bus error and arbitration lost with detailed bit
  • position
  • Supports test cases as per standard
    • CiA 610-2 - Conformance test plan for CiA 610-1
    • CiA 611-2 - Conformance test plan for CiA 611-1
  • Supports SDU types as per 611_1v00000701.pdf specification.
  • Supports programmable clock output
  • Supports single-shot transmission
  • Supports self-reception of own messages
  • Supports message acceptance using single filter and double filter
  • Supports TEC/REC error count registers with read/write access
  • FD CAN support minimum is 25Mhz (i_clk) frequency, typically supports up to
  • 100Mhz.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the CAN XL Controller IP. Ports of core module are the top level ports for the CAN XL Controller IP.

TFSM: TFSM Module is responsible for driving CAN frames through Bus. Standard and Extended Message formats transactions for CAN ,CAN FD and CAN XL frames. Response frame transactions, If remote frame was received.

RFSM: RFSM Module is responsible for sampling CAN, CAN FD and CAN XL frames through Bus and also for Error detection.

TIMING: TIMING Module is responsible for Bit timing characteristics of CAN protocol.and also for BRS(Bit rate switching) in CAN FD and CAN XL Scenarios.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 12nm25.61K100MHz
TSMC 28nm17.39K100MHz
TSMC 90nm25.24K100MHz
TSMC 130nm25.24K100MHz
TSMC 180nm26.91K100MHz
UMSC 55nm29.85K100MHz
SMIC 40nm18.70K100MHz
GF 180nm18.41K100MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e1500 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.