MIPI RFFE Master IIP

• Compliant with version 3.0 MIPI RFFE Specifications
• Full MIPI RFFE Master Functionality
• Supports following frames,
• Command Frame
• Data/Address Frame
• No Response Frame
• Bus ownership transfer
• Interrupt polling
• Master write and read
• Master context write and context read
• Supports extended register read/writes
• Supports interrupt summary and identification command sequence
• Supports Master ownership handover
• Support Master write and read sequence
• Support Trigger and Extended trigger modes
• Support Masked write command sequence
• Support Silent Master initiated bus park
• Supports Bus Clocked Condition
• Supports Timed Trigger
• Supports Mappable Triggers
• Support Synchronous read
• Supports Low power testing
• Bus-accurate timing
• Supports half speed
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors
• Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like RFFE or SPI or I2C Interface
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

CORE: Core module interconnects all the sub-modules in the MIPI RFFE Master IP. Ports of core module are the top level ports for the MIPI RFFE Master IP.

START: Start module detects the Sequence Start Condition (SSC) on the RFFE bus. Start detect signal from this module triggers the non-bom FSM to collect and respond to transcations.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for RFFE.

CSR: CSR module has all the control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

SFSM: This sfsm works when master receives the commands from the another BOM master.

ARB(Arbiter): Provides priority based access to the CSR module for the two FSM modules.

DRIVE: Driver module is responsible for driving any data on RFFE bus from RTL Master.When RTL Master is a BOM,it needs to drive the data from FSM module in “i_pre_com_scl” clock in SDA line.When the RTL master is a non BOM device,it needs to drive the data from SFSM module in “i_scl” clock in SDA line.

FSM: In RFFE Master core, FSM module is responsible for driving commands on to the RFFE bus after Master won the arbitration and it reads required the command and data from CSR Block. When FSM samples the read data from other devices, it writes the received data into CSR Block.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.