CORE: Core module interconnects all the sub-modules in ETHERNET 50G PCS IP. Ports of core module are the top level ports for the ETHERNET 50G PCS IP.
TRANSMITTER: It performs the 64B/66B encoding and scrambled data to transmits 66bit block data. It constructs the 257 bits of block using 256/257 transcoder.
ALIGNMENT INSERTION: This block periodically insert the special alignment markers in the data stream for all lanes.
BLOCK DISTRIBUTION: This block is used to distributes the 66bit data block to the four lanes.
FEC TRANSMITTER: The FEC transmitter constructs the FEC block and perform the FEC transcoding, and than scrambling FEC encoded data.
FEC ENCODER: This block does the FEC encoding on the FEC transcodeing data and adds the FEC parity at the end of the each FEC block.
GEARBOX TX FIFO: This FIFO module stores Tx data and process the data with the different read and write clock domain based on the PMA width.
GEARBOX TX: The Tx gearbox module is a digital logic block used to adapt data between two different bus widths and clock frequencies based on the PMA width.
GEARBOX RX: The receive gearbox module is used to adapt the data between two different bus widths and clock frequencies, based on the PMA width.
GEARBOX RX FIFO: This FIFO module stores Rx data and process the data with the different read and write clock domain based on the PMA width.
BLOCK SYNC: The block synchronizer is used to detect the valid 66bits of data block for the all lane, when FEC enable is deasserted.
BER: The BER monitor continuously monitors the input data and validates whether it receives a valid sync header.
ALIGNMENT LOCK: This block used lock the alignment marker pattern for each lane after receiving the block lock 66bit data.
LANE DESKEW: This block align the all received lane using lane deskew logic after found the alignment marker.
FEC INTERLEAVING: This block is used to rearrange the data, so that consecutive bits are spread across the different codewords.
FEC RECEIVER: The FEC receiver implements the FEC lock FSM and descrambling the FEC data and checks the FEC parity and performs the FEC detranscoding.
FEC DECODER: This block process to check the FEC parity and decode the FEC descrambling data. ALIGNMENT REMOVAL: This block revomes the special alignment markers in the data stream for all the lane.
RECEIVER: The Receiver process the 256/257 detranscoding than descrambling and 64B/66B decoding of the 66bit valid input data.
AN ARBITER: This block is implemented to AN state transistion to the final resolution, which will be process the information between the DME TX and DME RX to provides the AN process.
AN DME TX: This block handles the transmitter DME pages after that encodes the AN DME page.
AN DME RX: This block after DME page decoding handles the reception of AN DME page.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
