The SivaKali Tech SSRAM Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Optimized for high-performance computing, storage appliances, and mobile SoCs. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Maximum Bandwidth: Intelligent controller architecture maximizes bus utilization and minimizes latency.
Data Integrity: Advanced ECC (Error Correction Code) and reliability features for enterprise-grade data protection.
Broad Compatibility: Supports a wide range of JEDEC standard memory devices from major vendors.
PHY Independent: DFI-compliant interface allows easy integration with third-party or foundry-provided PHYs.
FEATURES
Supports SSRAM protocol standard Specification
Supports all the SSRAM commands as per the specs
Supports Automated power down when deselected
Two request ports to allow two requesters to share access to the SSRAM devices
Synchronous SRAM organized as 2Meg words x 48bit
Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations
Supports 40MHz to 133MHz bus operations
"ZZ" Sleep Mode option for partial power-down
Four Word Burst Capability linear or interleaved
Internally self-timed output buffer control eliminates the need for asynchronous output enable
8 Chip select signals to access up to 8 memory banks
Independent programmable timing parameters for each chip select
Independent address mapping for each chip select
Supports write cycles operation
Supports read cycles operation
Supports complete static memory without clock and timing strobe
Supports equal address and chip enable access times
Supports following device types
X4, X8, X16, X32
Independent programmable data width of 8, 16 and 32 bits for each chip select
Supports 32-bit and 64-bit user interface bus width
Supports burst access from the request ports
Automatic issues multiple accesses to memory device (byte collection) to match data word size of memory device with user interface data width
Optimized for logic synthesis for ASIC and FPGA implementations
Fully static design with edge triggered flip-flops
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the SSRAM Controller IP. Ports of core module are the top level ports for the SSRAM Controller IP.
FSM: SSRAM Controller IP FSM manages control signals, to control read/write flow. Ensures SSRAM timing requirements like access time, setup time, hold time, and write pulse width. Also controls data direction by switching the data bus between input and output during reads and writes.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System Clock Frequency
TSMC 28nm
24.04K
50MHz
FPGA Device and Family
Logic Resources
Clock Frequency
AMD-xcvu9p-flga2104-2L-e
51685 LUT's
187.25MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
