Skip to main content
Skip to main content

eMMC Device Controller IIP

Embedded Multi Media Card Device Controller IIP

eMMC Device Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech eMMC Device Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Optimized for high-performance computing, storage appliances, and mobile SoCs. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Maximum Bandwidth: Intelligent controller architecture maximizes bus utilization and minimizes latency.

Data Integrity: Advanced ECC (Error Correction Code) and reliability features for enterprise-grade data protection.

Broad Compatibility: Supports a wide range of JEDEC standard memory devices from major vendors.

PHY Independent: DFI-compliant interface allows easy integration with third-party or foundry-provided PHYs.

FEATURES
  • Compliant with JESD84-B51 Specification and earlier versions
  • Compliant with JEDEC eMMC CQHCI for Command Queuing
  • Supports different data bus width modes: 1-bit, 4-bit, 8-bit
  • Supports Command queuing
  • Supports Enhanced Strobe
  • Supports higher than 2GB densities of memory
  • Supports Replay Protected Memory Block (RPMB) functionality
  • Supports packed Write/Read commands
  • Supports High Priority Interrupt (HPI) Mechanism
  • Supports send tuning block (CMD21) command
  • Supports Single and Dual Data Rate Timing for Read/Write Operations
  • Supports HS200 and HS400 Modes
  • Supports Single byte, Single block ,Multi –block(finite and infinite) transfers and MMC
  • Supports CRC7 checking for command and CRC16 for Data integrity
  • Supports Password protection for Cards
  • Supports extended security protocols commands
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the eMMC Device Controller IIP. Ports of core module are the top level ports for the eMMC Device Controller IIP

CSR: CSR Module has all the registers and configurations.RCA – Relative Card ,CID – Card identification register,CSD – Card Specific Data ..etc. We can read/write csr registers using software interface

DMA Controller: The sampled write data of Dshifter will be written in the write FIFO which is done by Dshifter module. DMA controller reads the data written in the write FIFO and writes that data into the SoC Master , only if the CRC is matched. DMAcontroller reads the data from SoC Master and writes in the read FIFO. DShifter reads the data from read FIFO and drives that data to the connected ports.

CMD FSM: CMD FSM module has the eMMC Functional State Machine.Responses will be generating in the module. State of the eMMC card will be move based on the commands received.If the unsupported commands receivced or the commands are not met theexpected condiotns card status will be update. Current state,erase sequence error,illegal command will be updating to card status register. When set bus width command received sd status register will be update by this module. Once the response has been generated length of the response and delay of Ncr is updating by this module

DATA FSM: DATA FSM Module has the operation of write and reading of the data. Busy intimation for the write data will be send by this module to the DSHIFETR module. If crc error occurs FIFO will be flushing using this module.Erase operation also done in this module. If abort received moving to the idle state.

CSHIFTER: Cshifter module samples the command from the host and driving the response which for the command received.

DSHIFTER: DSHIFTER Module samples write data and drives read data according to the commands.

LOCK: Lock/Unlock data will be processed by this module. Password match/mismatch,set/reset,erase,lock/unlocking the card were supported by this module.Lock/unlock failed error is supported by this module and updating in card status register.Old password from the CSR is checking with the new password received for the lock/unlock command . Setting the password for the locking card is done in this module If the password is mismatch lock/unlock bit will be set in the cardstatus register. If the abort command received not accepting the lock/unlock data.

PROGRAM CSD: Received CSD data will be send to the CSR using this module. If the abort command received, it will not accept the program csd data.The process of all the bits in CSD register is done by this module. Status of the CSD data will be updating to the CFSM module

Minimum COMMAND DELAY: Minimum command delay module calculates the command delays like N CC, N CR, N RC, and N ID. It gives the enable for the in between delay. When the delay gets completed it gets down and ready to do the transfers.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem clock frequencyeMMC clock frequency
TSMC 28nm50.01K50Mhz50Mhz
TSMC 180nm76.15K50Mhz50Mhz
TSMC 130nm72.57K50Mhz50Mhz
TSMC 90nm72.57K50Mhz50Mhz
TSMC 12nm74.93K50Mhz50Mhz
UMSC 55nm87.12K50Mhz50Mhz
SMIC 40nm52.58K50Mhz50Mhz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.