The SivaKali Tech AES IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Essential for safeguarding sensitive data in government, financial, and IoT applications. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Side-Channel Resistance: Design hardened against DPA (Differential Power Analysis) and other side-channel attacks.
High Performance: High-throughput encryption/decryption engines to match line-rate speeds of modern interfaces.
Standard Compliance: Fully compliant with NIST and ISO security standards.
Easy Integration: Standard system bus interfaces for straightforward integration into secure enclaves.
FEATURES
Fully compliant with the NIST FIPS 197 Advanced Encryption Standard specification and ensures standard-adherent operation across all supported configurations.
Compatible with user-programmable key sizes of 128, 192 and 256 bits.
Dynamically programmable for multiple cipher modes: ECB, CTR, CBC, CFB, OFB, GCM, CCM, LRW and XTS.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION
CSR: Contains all configuration registers used to monitor status and control the RTL functionality.
AES: A unified encryption engine that consolidates all standard operating modes into a single hardware block, allowing for dynamic mode selection based on user configuration.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
Cipher Clock Frequency
TSMC 28nm
84.34K
40MHz
SMIC 40nm
88.65K
40MHz
UMC 55nm
138.82K
40MHz
FPGA Device and Family
Logic Resources
Cipher Clock Frequency
AMD-xcvu9p-flga2104-2L-e
14775 LUT's
40MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
