CORE: Core module interconnects all the sub-modules in the Ethernet 100BASE-TX IP. Ports of core module are the top level ports for the Ethernet 100BASE-TX IP.
TX FSM: TX FSM module is used to implement both encapsulation and 4B/5B encoding of the MII data.
PCS_ENC_4B_5B:
PCS_ENC_4B_5B module is used for encoding the four bit data into five bit code groups.The PCS comprises the Transmit, Receive, and Carrier Sense functions for 100BASE-T. PMA_TX: The PMA TX module collects 5bit code group send does NRZ-NRZI conversion and drives the 5bit NRZI data Optionally,It will supports transmission the Far-End Fault Indication.
PMD_TX: It will do the NRZI-NRZ conversion and gives the NRZ bit to scrambler.
SCR_TX: This module performs scrambling operation for the received NRZ data.
MLT3_ENC: This module performs the MLT3 encoding and drives to MDI(Media Dependent Interface).
TX_SLEEP_TIMER: TX LPI Timer module has two timers as sleep, quiet. These timers are used for EEE capablity to save power.
MLT3_DEC: This module receives the MLT3 encoded data from MDI(Media Dependent Interface) and perfroms MLT3 Decoding and code group alignment.
DESCRAMBLER_RX: This module will receive the aligned data and performs the IDLEs(1s) detection and NRZ-NRZI conversion and descrambles the code groups.
PMA_RX: In performs NRZI-NRZ conversion with respect of the carrier and fault detection. It LOCKs descrambler seed from the received data.
PCS_DEC_5B_4B: It performs 5B/4B decoding and wait for the start code groups for the packet detection.
RX_LPI_TIMER: RX LPI Timer module has three timers as sleep, quiet and wake These timers are used for EEE capablity to save power.
RX_FSM: RX FSM module is used to decapsulates the data and drives to MII.
CARRIER SENSE: In this module the carrier sense signal is asserted when if any one of the transmitter starts transmitting frame or receiver starts receiving frame.
LINK_MONITOR: The LINK_MONITOR module process monitors signal_status and updating the link status.
CSR: CSR module has Control Status registers that controls the IP all the registers. The contents of the registers are decoded and assigned to its respective output port based on its functionality.
