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ARINC429 CONTROLLER IIP

Aeronautical Radio Incorporated 429 Controller IIP

ARINC429 CONTROLLER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ARINC429 CONTROLLER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Engineered for ADAS, infotainment, and vehicle control units (ECUs). Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Automotive Grade: Developed with ISO 26262 functional safety processes (ASIL-B/D Ready).

High Reliability: Robust error handling and fault tolerance for mission-critical vehicle networks.

Legacy & Future: Supports both classic protocols and modern, high-speed automotive networking standards.

Cost Effective: Affordable licensing for high-volume automotive production runs.

FEATURES
  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports and implements ARINC SPECIFICATION 429 PART 1-17.
  • Supports all word structures and protocol necessary to establish bus communication as per the specs.
  • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus.
  • Supports LRU with multiple transmitters and receivers communicating on different buses.
  • Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself.
  • Supports Transmission rates at either a low speed 12.5 kHz or a high-speed 100kHz.
  • Supports two speeds for data transmission
    • Low speed operation 12.5 kHz, with an actual allowable range of 12 to 14.5 kHz.
    • high-speed operation is 100 kHz.
  • Supports bipolar and Return-to-Zero encoding format.
  • Supports following data types
    • Binary BNR Transmitted in fractional two's complement notation
    • Binary Coded Decimal BCD Numerical subset of ISO Alphabet No. 5
    • Discrete Data Combination of BNR, BCD or individual bit representation
    • Maintenance Data and Acknowledgement Requires two-way communication
    • Williamsburg/Buckhorn Protocol A bit-oriented protocol for file transfers
  • Supports duplex or two-way communication in Maintenance Data and Acknowledgement between source and sink.
  • Supports error detection mechanics
  • Fully synthesizable
  • Static synchronous design
  • Edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontrollerdevices
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
  • Glitch injection and detection
  • Status counters for various events.
  • FIFO depth programmable.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ARINC429 Controller IP. Ports of core module are the top level ports for the ARINC429 Controller IP.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for transmission and reception of ARINC429 Controller.

SOURCE_FSM: Source fsm module implements ARINC429 Source controller state machine.

SINK_FSM: Sink fsm module implements ARINC429 Sink controller state machine.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock Frequency
TSMC 28nm8.11K50MHz
UMC 55nm13.36K50MHz
SMIC 40nm7.75K50MHz

FPGA Device and FamilyLogic ResourcesSystem Clock Frequency
AMD-xcvu9p-flga2104-2L-e12525 LUT's50MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.