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AHB Multilayer Interconnect IIP

AHB Multilayer Interconnect IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech AHB Multilayer Interconnect IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Forming the high-speed communication backbone of complex System-on-Chips. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Deadlock Free: Robust routing logic prevents system hang-ups under heavy load conditions.

Low Latency Bridging: Efficient clock domain crossing and protocol conversion with minimal cycle overhead.

High Frequency: Pipelined architecture designed to close timing at high clock frequencies in modern nodes.

Scalable: Easily configurable for simple bus fabrics or complex, multi-layer network-on-chip (NoC) implementations.

FEATURES
  • Compliant with AMBA AHB specification
  • Supports configurable number of AHB Master Supports configurable number of AHB Slave Supports standardized user interface signals for easy integration with any IP
  • Supports control logic to map User Interface signals with the AHB signals
  • Supports configurable Data and Address Bus
  • Supports user-defined Slave to Master mapping
  • Supports user-defined Slave address per Master
  • Round-robin or priority based arbitration selectable per Slave
  • Higher throughput and less arbitration overhead between Masters as arbitration is done at each Slave port
  • Supports all protocol transfer types, burst transfers and response types
  • Support for all the transfer sizes
  • Supports configurable Endianness of the Data bus
  • Supports locked transfers
  • Supports early burst termination on receiving Error response from Slave
  • Supports two cycle error response in Slave
  • Supports response generation with wait states in Slave
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION

CORE: Core module performs all the below functionalities in the AHB Multilayer Interconnect IIP.Ports of core module are the top level ports for the APB2AHB BRIDGE IP. It Receives the APB read/write transactions and translates them into corresponding AHB transfers.

AHB SLAVE: Acts like an interconnect which receives transfers from User interfaces and send in to Interconnect matrix through decoder.

AHB MASTER: Presents in slave side interface to receive the transactions from interconnect matrix, process them and send them to Slave user interfaces.

DECODER: Identifies the target slave based on address issued by the master. It generates select signals to route the transactions to respective slaves.

INTERCONNECT MATRIX: AHB MLIC Interconnect matrix connects multiple AHB Masters to multiple slaves, allowing parallel and independent data transfers between different master-slave pairs.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic Resources
TSMC 12nm8.23K100MHz
TSMC 28nm5.16K100MHz
TSMC 90nm7.51K100MHz
TSMC 130nm7.51K100MHz
TSMC 180nm7.95K100MHz
GF 180nm5.79K100MHz
SMIC 40nm5.49K100MHz
UMC 55nm9.48K100MHz

FPGA Device and FamilyLogic Resources
AMD-xcvu9p-flga2104-2L-e860 LUT's100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.