MIL_STD_1773 CONTROLLER IIP

• Implemented in Unencrypted Verilog, VHDL and SystemC
• Compliant with MIL-STD-1773 Standard.
• Supports configurable length of word length, default 20 bits.
• Supports configurable length of data bits, default 16.
• Supports configurable message length per transfer.
• Supports NRZ and Manchester encoding.
• Supports single or multi bus control.
• Supports following message formats
• Controller to terminal
• Terminal to controller
• Terminal to terminal
• Broadcast
• System control
• Glitch injection and detection
• Supports up to 31 remote terminals
• Supports all types of errors insertion/detection as given below:
  • Command word sync error
  • Data word sync error
  • Status word sync error
  • Command word parity error
  • Data word parity error
  • Status word parity error
  • NRZ or Manchester encoding error
  • Bi-phase encoding error
  • Low bi-phase encoding error
  • High bi-phase encoding error
  • Oversize data word error
  • Undersize data word error
  • Extra data words error
  • Less data words error
  • Various illegal command errors
  • Inter message gap error
  • Terminal response timeout error
• On-the-fly protocol and data checking.
• Status counters for various events on bus.
• Built in functional coverage analysis.
• Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
• FIFO depth programmable.
• MIL STD 1773 Verification IP comes with complete test suite to verify each and every feature of MIL STD 1773 specification.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the MIL_STD_1553 IP. Ports of core module are the top level ports for the MIL_STD_1553 IP.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for MIL_STD_1553.

FSM: FSM module generates the MIL_STD_1553 transactions on MIL_STD_1553 based on commands from CSR block. This blocks implements all the features of MIL_STD_1553 specs.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ENCODER: This module is used to drive the data with Manchester encoding and send the data onto the MIL_STD 1553 Interface

DECODER: This module is used to sample the data from the MIL_STD Interface and decodes the Manchester code.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.