The SivaKali Tech RapidIO Switch IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.
COMPETITIVE ADVANTAGE
Production Proven: Validated in silicon and FPGA across diverse applications.
Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.
Expert Support: Direct access to senior design engineers for rapid integration assistance.
Flexible Deliverables: Available as synthesizable source code or optimized netlists.
FEATURES
Compliant with RapidIO Interconnect Specification 2.0, 2.1, 2.2.
Supports 1.25 Gbaud, 2.5 Gbaud lane rate.
Support for up to 4 ports.
Supports 1x/2x and 4x Physical lanes.
Supports 66, 50 and 34-bit addressing on the RapidIO interface.
Supports 8b/10b encode and decode functions.
Supports scrambler/descrambler.
Supports all types of packets and sizes.
Supports all types of IDLE sequences, Control and Status Symbols.
Supports 8-bit and 16-bit device IDs.
Automatic freeing of resources used by acknowledged packets.
Supports communication with mailboxes via messages.
Supports generation and reaction to flow control.
Supports out of order transaction delivery based on the prioritization.
Supports critical request flow ordering.
Supports all capability (CARs) and configuration and status registers (CSRs)
Supports interrupt for each error detection and for complete serial message reception
Supports DMA(Optional)
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION
CORE: Core module interconnects all the sub-modules in the RapidIO switch IP. Ports of core module are the top level ports for the RapidIO switch IP.
ADDRESS LEARNING: The Address Learning Module extracts destination addresses from packets, maps them to pre-loaded ports, and routes packets accordingly.
MAC: This module is used for handling packet framing,deframing,link-level control, flow control, error checking, and reliable data transfer between switch ports.
ARBITER: This module is used for resolving multiple simultaneous requests and grating controlled, priortized access to a shared resource.It is used to collect the data from soc slave interface.
ASIC AND FPGA IMPLEMENTATION
ASIC Technology
Logic Resources
System clock frequency
Link clock frequency
TX serdes clock frequency
RX serdes clock frequency
AXI clock frequency
TSMC 28nm
200K
100MHz
156.250MHz
156.250MHz
156.250MHz
156.250MHz
SMIC 40nm
240K
100MHz
156.250MHz
156.250MHz
156.250MHz
156.250MHz
UMSC 55nm
430K
100MHz
156.250MHz
156.250MHz
156.250MHz
156.250MHz
FPGA Device and Family
Logic Resources
System clock frequency
Link clock frequency
TX serdes clock frequency
RX serdes clock frequency
AXI clock frequency
AMD-xcvu9p-flga2104-2L-e
33333 LUT's
100MHz
156.250MHz
156.250MHz
156.250MHz
100MHz
LICENSING OPTIONS
Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.
