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HMC IP

Hybrid Memory Cube IP

HMC IP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech HMC IP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Supports 100% of HMC protocol standard 1.0,2.0 and 2.1
  • Supports all the HMC commands as per the specs.
  • Supports 2,4 and 8 link configuration
  • Supports half_width(8-lanes) and full_width(16-lanes)
  • Supports 16, 32, 48, 64, 80, 96, 112, 128 and 256 byte request Supports 12.5 Gb/s, 15 Gb/s, 25 Gb/s, 28 Gb/s, or 30 Gb/s SerDes I/O interface
  • Supports Packet-based data/command interface
  • Supports Poison packets handling
  • Supports scrambler and descrambler
  • Supports Training Sequence
  • Supports lane reversal and polarity inversion
  • Supports all block size setting
  • Supports flow control
  • Supports link retraining
  • Supports packet retry
  • Supports write data mask and data strobe features.
  • Supports 4GB/8GB configuration
  • Supports Internal ECC data correction and Error detection (cyclic redundancy check [CRC]) for packets with automatic retry Supports Power management supported per link
  • Supports Built-in self-test (BIST)
  • Supports JTAG interface (IEEE 1149.1-2001, 1149.6)
  • Supports I2C interface up to 1 MHz
  • Supports SPI master interface
  • Fully synthesizable
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the HMC Controller IP. Ports of core module are the top level ports for the HMC Controller IP.

FSM: HMC FSM is a packet-oriented logic unit. It orchestrates the flow of serialized data packets across multiple high speed links. This involves a sophisticated initialization process where the FSM manages Link Training to ensure all data lanes are perfectly synchronized before any memory operations begin.

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock Frequency
TSMC 28nm24.04K50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.