CORE: Core module interconnects all the sub-modules in the Manager IP. Ports of core module are the top level ports for the Manager IP. The Core Module acts as the central interconnect hub that integrates and coordinates all the sub-modules within the SoundWire I3S Manager IP.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
ML_SM: The Manager Link State Machine (ML_SM) module implements the state control logic for the SoundWire Manager Link layer. It follows the MIPI SoundWire specification, governing link bring-up, configuration, and runtime management.
Presclaer: Prescaler module is used to divide the i_swi3s_clk clock based on the given prescaler value to derive the serial clock pre_com_clk.
US TIMER: The Microsecond Timer (US Timer) module generates the us tick pulse every microsecond width used for microsecond-resolution timing operations within the Manager IP.
CDS: CDS module is for Control Data Stream. Control Data Stream is to transfer information in both directions between the Manager and Peripherals. This block implements 8b/10b encoder, 10b/8b decoder, serializer and deserializer.
CTP: This module implements Command Transport Protocol state machine. The state machine sends the commands PING, WRITE, READ, ANNOUNCE and other commands as per specs, process the responses, retry failed transfers.
PTL: The Payload Transport Layer (PTL) Module handles streaming data payloads such as audio samples. It provides a structured channelized architecture for multiple datastreams and integrates DPort submodules for each channel.
DPORT: The Data Port (DPort) Module manages the source and sink logic for data streams.Each DPort operates as a programmable state machine that controls sample flow based on channel configuration.
SCRAMBLER: The Scrambler Module performs data scrambling and descrambling functions to minimize DC bias and EMI on the transmission line. This ensures balanced data patterns and compliant signal characteristics on the SoundWire I3S physical interface.
MAPPER: The Mapper Module performs mapping of audio sample data and control bits between logical data channels and the PHY interface. It defines how samples are serialized and transmitted over the link.
FIC: This module implements MIPI Soundwire I3S FIFO controllers for all Data Ports FIFO Command FIFO and Response FIFO.
PHY IF: The Physical Interface (PHY_IF) Module drives and samples data at the physical layer according to the SoundWire I3S protocol. It is responsible for electrical-level interfacing and NRZ encoding/decoding.
