CORE: Core module interconnects all the sub-modules in the Controller IP. Ports of core module are the top level ports for the Controller IP.
PRESCALAR: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for I2C.
MFSM: Master FSM module process the commands once pending request from CSR and the bus is enabled. For Example: I2C write, Master FSM will send Slave address, R/W bit, Write data and waits for ACK/NACK from Slave.
SFSM: SFSM module process I2C/SMBUS Slave commands once start is detected. SFSM responds to I2C/SMBUS Slave commands (ACK/NACK for Write transfer and Read data for read transfer) only if Slave address is matched with the address driven on the i_sda bus by the Master.
ARBITER: Arbiter Module is to arbitrate from which module has to access FIFO data from the CSR Module. When the Master acts as Current Master, Master FSM module will access the FIFO data from the CSR Module. When the Master acts as Non-Current Master, Slave FSM module will access the FIFO data from the CSR Module.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
DMA: This module implements I2C controller functionality. Based on configuring DMA_EN we can enable the DMA process. DMA module fetches data from DMA memory to process and loads the sampled data into DMA memory with use of SoC Master Interface.
START DETECTION: Start module detects the start condition on bus based on SDA and SCL line. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. Start module detects the start condition on I2C bus. Start detect from this module triggers Slave FSM, to process an I2C transaction.
STOP DETECTION: Stop module detects the stop condition on bus based on SDA and SCL line. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. Stop module detects the stop condition on I2C bus.
