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MIPI SPMI Master IIP

MIPI System Power Management Interface MASTER IIP

MIPI SPMI Master IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech MIPI SPMI Master IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Ideal for mobile, automotive, and IoT applications requiring high-bandwidth camera and display interfaces. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Power & High Efficiency: Optimized for mobile and battery-operated devices with advanced power gating and low-leakage architecture.

Silicon Proven: Validated on leading foundry nodes (5nm, 7nm, 12nm, 28nm), ensuring reduced integration risk.

Comprehensive Support: Full compliance with latest MIPI Alliance specifications, including CSI-2, DSI-2, and I3C.

Flexible Licensing: Cost-effective, royalty-free licensing models compared to restrictive tier-1 vendor options.

FEATURES
  • Supports 2.0 and 1.0 MIPI SPMI Specification
  • Full MIPI SPMI Master functionality
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports ACK/NACK as per 2.0 specs
  • Glitch suppression (optional).
  • Supports transfer Bus Ownership Command Sequence.
  • Supports Connect/Disconnect Sequence.
  • In built Host controller interface for command queue based Master command processing (Optional). HCI contains DMA engine
  • Supports External DMA (Optional)
  • Support Master priority arbitration
  • Supports SCL frequency control
  • Supports multiple master and slaves
  • Supports extended register read/writes
  • Supports Baud rate control
  • Supports Low power modes
  • Supports wakeup command
  • Supports Authentication Command Sequence
  • Device Descriptor Block command Sequences
  • Supports baud rate control
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the MIPI SPMI MASTER IP. Ports of core module are the top level ports for the MIPI SPMI MASTER IP.

FSM : FSM module is responsible for driving commands on to the SPMI bus after Master won the arbitration and it reads required the command and data from CSR Block.

CSR : CSR module contains the configuration and status registers to configure the Master core, Master data memory, DDB Memory and Interrupt generation logic.

ARB : ARB module is responsible for connecting the Master to SPMI Bus after power up,monitoring Bus ownership status, Bus arbitration status and responsible for driving SSC and SCL when any Slave won the arbitration.

DARB : DARB module is responsible to perform arbitration between REQ,FSM,CORE and HCI access to CSR block.

SDA_OUT : SDA Out module is responsible for driving all data onto SPMI bus from DUT.

SLAVE FSM : Slave FSM module is responsible for handling the Master receiving commands initiated by other SPMI devices.

REQ : REQ module is responsible for driving data in Connect phase and Master arbitration phase, generating arbitration result (won/lose) to ARB Block, maintain MPL (Master Priority Level) value for multi master environment, and traces the bus fully to find out the bus free condition

START : Start module detects the SSC and arbitration start condition on SPMI bus.

HCI : HCI module contains the SPMI Host controller FSM.

PRESCALER : Prescaler module is responsible for clock division.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencySCL Clock Frequency
TSMC 12nm41.75K100MHz24MHz
TSMC 28nm28.28K100MHz24MHz
TSMC 90nm40.24K100MHz24MHz
TSMC 130nm40.24K100MHz24MHz
TSMC 180nm42.53K100MHz24MHz
GF 180nm30.81K100MHz24MHz
SMIC 40nm30.44K100MHz24MHz
UMC 55nm50.63K100MHz24MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencySCL Clock Frequency
AMD virtula ultrascale6093 LUT's24MHz100MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.