ETHERNET TOE 10G IIP

• Compliant with IEEE 802.3.2022,rfc 793 for TCP and rfc 791 for IP specification
• Full duplex TCP/IP, High-speed both transmission and receiving
• Enhanced automatic functions,
• --> TCP sequence number generation
• --> TCP checksum and insertion
• --> Window buffer and data re-send function
• --> IP header checksum generation
• --> IP header generation
• Support TCP/IPv4 protocol
• Optional Jumbo frame support
• Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
• Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
• Supports both server and client mode (Passive/Active open and close)
• Supports XGMII Interface
• Supports MDIO (Clause 22 and Clause 45) Interface
• Supports Programmable Inter Packed Gap(IPG) and Preamble length
• Supports transmit and receive FIFO interface
• In house UNH compliance tested
• Optional support for DMA support for both transmit and receive side
• Optional support for IEEE Standard 1588-2008 PTP
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core module interconnects all the sub-modules in the Ethernet TOE 10G IP. Ports of core module are the top level ports for the Ethernet TOE 10G IP.

TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.

GMII/MII TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC 1G Interface by encapsulating the Ethernet packet and frame headers.

FLOW CTRL: Initiating the Transmission of pause frame-based on the Receive FIFO's threshold or External requests.

PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

GMII/MII RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.

RX CTRL: Receive Control block processes the data from MAC 1G interface and push the data into RX ASYNC FIFO

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames.

MAPPER: This block samples and control the RoE packets, adding the necessary RoE headers, like flow ID, sequence number and length.

DEMAPPER: The Demapper performs receives the ethernet and RoE headers, and validates the flow ID and checks the packet loss using the sequence number.

CSR: CSR module has Control Status registers that controls the IP all the registers. The contents of the registers are decoded and assigned to its respective output port based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.