UCIe CONTROLLER IIP

• Supports specification version 1.0, 1.1, 2.0 and 3.0
• Supported Mode - Endpoint, Root Complex
• Supported Package - Standard package, Advanced Package
• Supported Protocol - PCIe, CXL, Streaming protocols (AXI, CXS, CHI)
• Supported Flit Formats
• Raw Format
• 68B Flit Format
• Standard 256B End Header Flit Format
• Standard 256B Start Header Flit Format
• Latency-Optimized 256B without Optional Bytes Flit Format
• Latency-Optimized 256B with Optional Bytes Flit Format
• Supports 4 GT/s, 8 GT/s, 12 GT/s, 16 GT/s, 24 GT/s, 32 GT/s, 48 GT/s and 64 GT/s speeds with:
  • 500 MHz, 1 GHz, 1.5 GHz, 2 GHz, 3 GHz, 4 GHz, 6 GHz and 8 GHz UCIe clock frequency
• Supports 800 MHZ speed for sideband data
• Supports 16 Lanes, 32 Lanes and 64 Lanes
• Supports Sideband messaging for link training and parameter exchange
• Supports Sideband Mailbox Mechanism for read and write configuration
• Supports Clock gating Mechanism
• Supports all handshake mechanism
• Check all DLLP fields and formatting
• Supports Data Link Feature Exchange
• Supports Link Power Management
• Supports Multi Stack protocol
• Supports all Vendor defined Sideband messages
• Supports UCIe Retimers
• Supports Flits CRC
• Supports Flit Retry
• Supports Positive edge clocking and no internal tri-states
• Scan test ready
• Fully synthesizable
• Static synchronous design
• Simple interface allows easy connection to microprocessor/ microcontroller devices
• Compliant with the latest ARM AMBA AXI3 and ARM AMBA AXI4 Protocol Specification
• Data Bus width configurable as 8,16,32,64,128,256,512 or 1024 bits wide
• Separate address, data & response phases. Separate read and write channels
• Support for burst-based transactions with only start address issued (Longer bursts up to 256 beats)
• Supports Increment Burst type
• Two versions of core available with one supporting multiple outstanding request with simultaneous access of write and read channel and the other that access either write or read at a time and not supporting outstanding request.
• Supports multiple outstanding request controlled by a Parameter
• Compliant with the latest ARM AMBA5 CHI specification (CHI-D)
• Support for Protocol, Network and Link layer communication, including flow
• control mechanisms across RN2HN and HN2SN links
• Supports all CHI protocol node types:
  • Request Nodes (RN-F, RN-D and RN-I)
  • Home Nodes (HN-F, HN-I and MN)
  • Slave Nodes (SN-F and SN-I)
• Support for skipping link initialization and retrying failed link initialization
• Configurable credit including dynamic and pre-allocated credit control
• Cache model support in Master and Interconnect (programmable). Monitor has backdoor access to these cache models
• Support for Speculative read and Snoop filtering
• Support for all Transaction types and Opcodes
• Supports Direct Memory Transfer and Direct Cache Transfer
• Supports Exclusive accesses, Cache Stashing, DVM Operations
• Supports Deallocating transactions, Poison and Data Check
• Supports all ARM AMBA5 CHI data widths
• Support for Request transactions with/without a Retry and cancelling of transactions
• Ability to issue multiple outstanding Non-snoopable/Snoopable transactions
• Programmable Protocol flit delays and different channels delays. Interconnect has the ability to replicate RN/SN inserted delays
• Supports all write/read responses and snoop responses
• Fine grain control of below:
  • Requester transaction including main memory access
  • Completer response to a Requester transaction and Requester
  • Acknowledgment/response to Completer's response
  • Interconnect generated snoop transaction to Snooped RNs
  • Interconnect generated main memory access transactions
  • Snooped RN response to a snoop transaction
• Supports fine grain control of response per address or per transaction
• Device and Normal memory types support
• Support for ordering of transactions/responses and reordering of data packets
• Support for error injection during Link initialization
• Ability to inject errors during transfers
• Supports constrained randomization of protocol attributes
• Programmable Timeout insertion
• Supports FIFO memory
• Rich set of configuration parameters to control CHI5 functionality
• Compliant with CXL 2.0/3.0/3.1 Specifications
• Implements CXL.io, CXL.mem, and CXL.cache protocols
• Supports ARB/MUX Link Management Packets (ALMP)
• Supports arbitration and data multiplexing/de-multiplexing
• Supports following CXL.cache/CXL.mem slots,
• Header slot
• Generic request/response slot
• Generic data slot
• Supports following CXL cache line,
• 32B Half cache line
• 64B Full cache line
• Supports following CXL flit type encoding,
• Protocol type
• Control type
• Supports all CXL.cache/CXL.mem request and response messages
• Supports all snoop responses
• Supports various framing errors
• Supports Multiple Data Header (MDH)
• Supports byte enable
• Supports CXL.cache/CXL.mem link layer retry
• CXL devices supports three types of resets
• Hot Reset
• Warm Reset
• Cold Reset
• Supports data poisoning
• Compliant with the latest ARM AMBA CXS specification
• Supports credit exchange mechanism
• Supports Link activation and deactivation
• Support for skipping link activation
• Configurable credit mechanism including dynamic and pre-allocated credit control
• Support for Interface properties and possible options as per protocol
• Supports continuous delivery of data - uninterrupted transmission of packets
• Flit packets placement
• Packet control fields
• Ability to configure the width of all signals
• Support for error injection during Link activation and deactivation
• Ability to inject and detect errors including:
  • Credit exchange mechanism
  • Parity
  • Packet size
  • Link activation and deactivation
• Programmable Protocol signal delays
• Rich set of configuration parameters to control CXS functionality
• Compliant with PCIe 6.0 Specifications
• Full PCIe Controller functionality
• Configurable timers and timeout
• Supports number of function, virtual channels, bus number and devices is one
• Supports Retry Mechanism
• Multiple Requester / Completer applications, including user supplied applications
• User interface for direct TLP queuing and receipt

CORE: Core module interconnects all the sub-modules and provides the top level ports for the entire UCIe Controller IIP.

CSR: CSR module has all the registers. It decodes configuration data and assigns it to specific ports to drive the IP's functionality.

ATU: Address translation unit module translates the UCIe address to csr address.

PROTOCOL LAYER: The protocol layer performs APB-to-UCIe bridge to transfer sideband data using UCIe sideband packet formats and also manages high-speed data communication by converting respective protocol data into UCIe mainband flits and reconstructing them on reception.

D2D ADAPTER: The D2D Adapter module manages both sideband and mainband communication by packing, and unpacking sideband packets, while packaging protocol data into protected flits for reliable high-speed transfer between local and remote dies.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.