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SAE J2716 Controller IIP

SAE J2716 Controller IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech SAE J2716 Controller IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Supports SENT standard specification SAE J2716 APRIL2016
  • Supports all types of frame reception
    • Short serial message format
    • Enhanced serial message format
  • Supports Enhanced serial message format with two different configurations
    • 12-bit data and 8-bit message ID
    • 16-bit data and 4-bit message ID
  • Supports all the fast channel data frame formats
    • Two 12-bit fast channels (6 data nibbles)
    • One 12-bit fast channel (3 data nibbles)
    • High-speed with one 12-bit fast channel (4 data nibbles, where only values 0-7 are used)
    • Secure sensor with 12-bit fast channel 1 and secure sensor information on fast channel 2 (6 data nibbles)
    • Single sensor with 12-bit fast channel 1 and zero value on fast channel 2 (6 data nibbles)
    • Two fast channels with 14-bit fast channel 1 and 10-bit fast channel 2 (6 data nibbles)
    • Two fast channels with 16-bit fast channel 1 and 8-bit fast channel 2 (6 data nibbles)
  • Supports programmable clock frequency of operation
  • Supports programmable length for nibble pulse period
    • Minimum nibble pulse period - 12 clock ticks
    • Maximum nibble pulse period - 27 clock ticks
  • Supports both 4-bit CRC and 6-bit CRC
  • Supports Alternative CRC calculation
  • Supports pause pulse properties
    • Minimum length - 12 clock ticks
    • Maximum length - 768 clock ticks
  • Supports extended pause pulse with up to 3333 clock ticks
  • Supports all types of error detection
    • Calibration error
    • Nibble low length error
    • Nibble high length error
    • Nibble minimum length error
    • Pause length error
    • Reserved bit error
    • Unique pattern error
    • Data nibble CRC error
    • Status nibble CRC error
    • H3 frame format error
    • H4 frame format error
    • H5 frame format error
    • Adjacent/Successive calibration error Supports interrupts for error detection and for complete serial message reception
  • Supports optional SPC protocol to enhances the SENT protocol
  • Supports all the 4 SPC transfer modes
    • Synchronous mode
    • Dynamic range selection mode
    • ID selection mode
    • Bi-directional mode
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the SAE_J2716 Controller IP. Ports of core module are the top level ports for the SAE_J2716 Controller IP

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock input for SAE_J2716 FSM Module and CRC Module.

FSM: FSM module receives the transactions from the SAE Bus and process the serial data.This blocks implements all the features of SAE_J2716 specs.

CSR: CSR module has all the Control registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

CRC: CRC Module calculates the CRC value based on the input data received from the FSM Module. Calculated CRC value sends to the FSM Module. Based on this CRC values the status registers are compared.

SYNC CELL: Two stage synchronizer module synchronize the incoming serial data input and sends the output to FSM module and the Prescaler module.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 28nm6.31K29.762MHz
UMSC 55nm11.86K29.762MHz
SMIC 40nm6.84K29.762MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e19766 LUT's29.762MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.