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USB2.x HUB IIP

Universal Serial Bus 2.x Hub IIP

USB2.x HUB IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech USB2.x HUB IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Perfect for consumer electronics, peripherals, and embedded IoT devices. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Certified Interoperability: Extensive testing against standard USB hosts and devices to guarantee plug-and-play compatibility.

Highly Configurable: Flexible endpoint configuration and FIFO sizing to optimize area vs. performance trade-offs.

Low Power Modes: Aggressive power management supporting Suspend/Resume and remote wakeup capabilities.

Legacy Support: Backward compatibility ensuring seamless operation with older USB revisions.

FEATURES
  • Compliant with USB 2.0 Specification
  • Supports High/Full speed using 8/16 bit UTMI/ULPI interface
  • Supports Optional PIO Mode for each endpoint (can be used for Interrupt endpoints)
  • Supports System bus Master/Target clock
  • Supports Endpoint Configuration
  • Configurable up to 15 downstream ports
  • Supports Bulk/control/ isochronous/interrupt transfers
  • Supports Dedicated control endpoint zero
  • Supports Configurable dual port RAM shared between endpoints
  • Supports USB Suspend/Resume support
  • Supports LPM
  • Support Remote wakeup
  • Supports STT (Single Transaction Translator) / MTT (Multiple Transaction Translator)
  • Supports one TT for all downstream facing ports that have full-/low-speed devices attached(STT)
  • Supports one TT for each downstream facing port (MTT)
  • Supports Downstream device connect/disconnect detection
  • Supports HS Repeater for the downstream HS device
  • Supports suspend and resume for power management
  • Support link power management
  • Supports test mode features.
  • various kinds of errors detection and handling
  • Supports CRC checking
  • Fully Synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors. Available as Additional Feature at extra cost
  • ISO26262 Functional safety(ASIL B/D)
  • ->ISO26262 Safety Manual (SAM) Document
  • ->ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA)
  • Document
  • Memories with ECC
  • Internal DMA
  • Basic Firmware – Linux Driver
  • Customer SoC I/F
FUNCTIONAL DESCRIPTION

RST_BLK: Reset block module is used to synchronizing the different reset.

CTRL: Controller module is used to perform the controller operation for the decoding of packet reception form host and acknowledging it respectively

LPM_XACT_ENG: LPM states (power management states) and mechanisms to affect state changes that are used by hubs to efficiently manage bus and system power in the Lpm transaction module

LPM_XACT_RCV: Lpm transaction receiver module is used to perform the transmission and reception operation for the low power management packets

TEST_DP: Test Data Packet module is used to perform the test mode data packet operations

FRAME_TIMER: Frame Timer module is used for the start of frame timings

HS_REPEATER: high-speed Repeater module repeats or transmits the received upstream datas to the corresponding downstream ports and vice vera.

FS_REPEATER: Full Speed Repeater module is used to perform the repeater operation for the full speed serial interface

PHY: Phy module is used to convert the serial data to 16-bit parallel data during receive and converts 16-bit data to serial data during transmit

COLL_DET: Collision Detect Module is used to detect collision of packets

SYNC_BLK: Synchronous block module is used to synchronizes the input to the destination clock

DOWN_PTR: Down Pointer module implements the downstream ports state machine

HIGHSPEED_HANDLER : high-speed Handler module is used to perform the translation operation the high-speed transactions

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesUTMI Clock Frequency
TSMC 28nm62.59k30MHz
UMSC 55nm110.34k30MMHz
SMIC 40nm66.08k30MHz

FPGA Device and FamilyLogic ResourcesUTMI Clock Frequency
AMD Virtex-7 FPGA(xc7vx485tffg1761-2)47532 LUT's30MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.