MIPI I3C Master HCI IIP

• Compliant with MIPI I3C version 1.2 and I3C HCI version 1.1 specifications.
• Compliant with JEDEC Module Sideband Bus version 1.0 specification.
• Compliant with MCTP I3C Transport Binding version 0.3.0 specification.
• Full MIPI I3C Master Functionality.
• Two wire serial interface up to 12.5 MHz using Push-Pull
• For I2C existing in a same I3C Bus, the supported speeds are,
• Fast Mode
• Fast Mode Plus
• Dynamic Addressing while supporting Static Addressing for legacy I2C device.
• Supports Master Pull up structures.
• Supports I3C address arbitration optimization.
• Supports Predictive addressing scheme
• Supports Direct commands
• Supports Direct command CCC framing
• Supports Single Data Rate (SDR) messaging.
• SDR with Direct CCC
• SDR with Broadcast CCC
• Supports High Data Rate (HDR) messaging
• HDR-Dual Data Rate Mode (HDR-DDR)
• In-Band Interrupt support and Hot-Join interrupt support
• Legacy I2C Device co-existence on the same Bus instance
• Direct Data interface support (PIO Mode)
• Command Queue for Command Descriptors
• Response Queue for Response Descriptors
• IBI Queue for both IBI status and IBI data
• DMA interface support (DMA Mode)
• Single transfer descriptor defines Command and Data
• Single response status descriptor reports status of the transfer
• Linked descriptor support (Multicast messaging support)
• Auto-Reject for In-Band Interrupt and Hot-Join (NACK and directed DISEC CCC to
• disable)
• DMA Mode with Command Rings, to enable clean Doorbell mechanisms
• Multiple Command/Response Rings and IBI Rings, including IBI payload
• Supports interrupt masking
• Supports Extended Capability Registers and Vendor specific registers
• Supports JEDEC specific CCC transfers
• Supports Packet Error code (PEC) for JEDEC specific transfers
• Supports MCTP command code specified in MCTP over SMBus specification
• Supports Fairness arbitration for MCTP
• Supports SDA stuck low recovery for MCTP
• Supports Write data and Command code NACK retry timer
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple host interfaces enable straightforward integration with microcontrollers and application processors.
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

CORE: Core module interconnects all the sub-modules in the Master IP. Ports of core module are the top level ports for the Master IP. SCL clock is derived from i_clk based on prescaler value.

PRESCALER: Prescaler module is used to divide the system clock based on the given prescaler value to derive the serial clock (SCL) input for I3C.

MASTER FSM: Master FSM module process the commands once pending request from CSR and host controller bus is enabled.For write transfer master FSM will send slave address, R/W bit,Write data and waits for ACK/NACK from slave.

CSR: CSR module has all the Host controller registers, Ring header registers for DMA mode and PIO registers for PIO mode. The contents of registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.