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JESD204C Receiver IIP

JEDEC Serial Data Interface 204C Receiver IIP

JESD204C Receiver IIP

Overview

1. Data Mode

2. Test Mode

COMPETITIVE ADVANTAGE

The SivaKali Tech JESD204C Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with JESD204 specification JESD204A, JESD204B.01 and JESD204C.1
  • Supports up to Subclass 0, 1, 2
  • Supports 1 to 8 lanes
  • Supports 1 to 64 converters per receiver
  • Supports frame sizes of 1, 2, 4, 8 and 16 octets per frame
  • Supports HD-mode
  • Supports 1 to 32 bit data width per converter
  • Supports CF = 0 and 1 control words per frame clock period per link
  • Supports 0 to 3 control bits per sample
  • Supports 1 to 8 samples per converter
  • Supports 1 to 32 frames per multiframe
  • Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample
  • Supports 0 to 15 Bank ID (BID)
  • Supports 0 to 255 Device Identification Number (DID)
  • Supports 0 to 7 Lane Identification Number (LID)
  • Supports reporting of various error statistics
  • Supports different Serdes interfaces 10, 20, 40, 60 bits and custom bits per lane
  • MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes) device supported
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors
  • JESD204B
  • Supports 10b/8b decoding
  • Scrambler can be enabled or disabled
  • JESD204C
  • Full JESD204C receive functionality
  • Supports up to Version A, B and C
  • Supports data rate up to 32 Gbps
  • Supports programmable clock frequency up to 32 GHz
  • Supports 66b/64b decoding
  • Supports 80b/64b decoding
  • Supports Forward Error Correction (FEC) and cyclic redundancy checks (CRC)
  • Supports single block, Multi block and extended multi block
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the JESD204B Receiver IIP. Ports of core module are the top level ports for the JESD204B Receiver IIP

TRANSPORT LAYER: The transport layer maps the conversion samples to non-scrambled octets. A set of samples and/or partial samples is grouped into a frame of F octets. Each sample is received as a group of N' bits, consisting of N data bits, optional control bits and optional tail bits

LINK LAYER: Link layer module is used to wait for the EMB lock and once it has received the actual data will be transmit to Transport layer

DESKEW: Deskew module is achieved by means of receive buffer delay which is used to achieve synchronization in all the lanes at a time

LANE: Lane module is used to received data, depending on the number of lanes the size of received data will get vary. In this block, input is based on serdes interface. Based on that the output will be generated and given to the PCS. The receiver first determines the sync header boundaries. Once this has been achieved, it descrambles the user data for the data link and decodes the sync header stream. Fill bits are not received in the 64B/66B encoding mode, and they are always ignored in the 64B/80B encoding mode

CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyCharacter Clock FrequencySerdes Clock Frequency
TSMC 12nm260K100MHz800 MHz3.2 GHz
TSMC 28nm182K100MHz800 MHz3.2 GHz
UMSC 55nm303K100MHz800 MHz3.2 GHz
SMIC 40nm192K100MHz800 MHz3.2 GHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e51685 LUT's187.25MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.