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V-By-One Receiver IIP

V-By-One high-speed (HS) Receiver IIP

V-By-One Receiver IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech V-By-One Receiver IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Delivering premium visual experiences for digital signage, broadcast, and consumer displays. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Quality Compression: Visually lossless compression algorithms optimized for minimal silicon area.

Real-Time Performance: Ultra-low latency processing suitable for live streaming and interactive applications.

Multi-Standard Support: Configurable to support various resolutions, frame rates, and color formats.

Power Efficient: Architecture optimized to minimize power consumption for portable multimedia devices.

FEATURES
  • V-By-One HS Version 1.4 Receiver
  • Fully compliant with the HS Version 1.2, 1.3 and 1.4 specification and ensures standard-adherent operation across all supported configurations.
  • Dynamically supports lane configurations of 1, 2, 4, 8, 16 and 32 lanes.
  • Supports link rates from 600Mbps to 4Gbps.
  • Dynamically supports multiple byte modes 3, 4 and 5.
  • Supports configurable output pixel processing of 1, 2, 4 and 8 Pixels Per Clock (PPC).
  • Supports programmable parallel interface widths of 20bits, 40bits and 80bits.
  • Supports maximum resolution up to 4k@240Hz.
  • Compatible with the video formats which are mentioned in V-By-One HS Version 1.4.
    • RGB 4:4:4 (18,24,30,36 Bits Per Pixel)
    • YCbCr 4:4:4 (18,24,30,36 Bits Per Pixel)
    • YCbCr 4:2:2 (16,20,24,32 Bits Per Pixel)
    • RGBW/Y 4:4:4:4 (32,40 Bits Per Pixel)
  • Performs the descrambler and 10b/8b decoder.
  • Supports lane deskew.
  • Supports color and control data mapping allocation to the 3D flag.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

GEARBOX: Reconstructs the variable 20bit, 40bit or 80bit parallel input data into a constant 20bit output data stream.

CDR PATTERN LOCK: Locks onto the Clock and Data Recovery (CDR) Training Pattern D10.2 (0101010101) within the received lane data.

COMMA DETECT: Locks onto the comma pattern in the received lane data to generate alignment data.

DECODER 10B/8B: Converts the incoming 10bit encoded data back into 8bit data.

DESCRAMBLER: Descrambles the lane data after 10b/8b decoding to reverse the EMI reduction formatting and recover the original payload.

DESKEW: Removes skew between the lanes and generates aligned lane output.

LINK FSM: Controls the receiver state machine and monitors the reception of both training patterns and normal video data.

HTPDN GENERATION: Generates the Hot Plug Detect (HTPDN) signal to communicate receiver readiness to the transmitter.

UNPACKER: Unpacks the lane data into standard pixel data based on the specific color format and color depth of respective lanes.

PIXEL MULTIPLEXER: Generates the standard video signals (hsync, vsync, vid_de, vid_ctl, vid_3dlr, vid_3den and vid_data) from the input pixel data, and manages the conversion to different output pixel per clock rates.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock FrequencySerdes Clock Frequency
TSMC 28nm21.19K100MHz297MHz200MHz200MHz
SMIC 40nm22.26K100MHz297MHz200MHz200MHz
UMC 55nm38.8K100MHz297MHz200MHz200MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock FrequencyLink Clock FrequencySerdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e5517 LUT's100MHz297MHz200MHz200MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.