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IEEE 1149.7 COMPACT TAP IIP

IEEE 1149.7 COMPACT TAP IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech IEEE 1149.7 COMPACT TAP IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES
  • Compliant with IEEE 1149.7 standard specification.
  • Supports TAP.7 capability classes T0 to T5.
  • Supports Reset and Selection Unit (RSU) for class T0 optional features.
  • Supports Extended Protocol Unit (EPU) for classes T0 to T3.
  • Supports all mandatory and optional EPU commands.
  • Supports Advanced Protocol Unit (APU) for classes T4 and T5.
  • Supports Transport function with 1 or 2 physical data channels (PDC) each supporting up to 16 data channel clients (DCC).
  • Supports 4 and 2 pin interface as specified in IEEE 1149.7 CJTAG.
  • Supports all mandatory and optional scan formats (JScan, MScan, OScan, and SScan).
  • IEEE 1149.7 Compact TAP supports following scan terminology
    • Data Register Scan.
    • Instruction Register Scan.
    • Control Register Scan.
    • Zero-Bit Scan.
  • IEEE 1149.7 Compact TAP supports following scan topology
    • Series scan topology : Class T0 - T5
    • Star-4 scan topology : Class T3 - T5
    • Star-2 scan topology : Class T4 - T5
  • Can be extended with user defines instructions and registers.
  • Fully synthesizable.
  • Static synchronous design.
  • No internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Cjtag Compact TAP IP. Ports of core module are the top level ports for the Cjtag Compact TAP IP.

CSR: CSR module has all the Control and status registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality. This block contains interrupt enable and status registers.

RSU: RSU module implements the Reset and Selection unit functionality. It is responsible for Resets, Start-up options, Escape detection, Selection alert and Deselection Alert processes.

EPU: This module is applicable to T1 and above TAP.7s. It has ZBS detection, Incrementing, locking, and clearing the ZBS count and its operating states.

APU: This module is applicable to T4 and above TAP.7s. The APU is inserted between the RSU and EPU to create both wide and narrow T4 and above TAP.7. Both the Standard and Advanced Protocols may be used with these TAP.7s.

FSM: TAPC state machine is present in this module. All state transitions of the TAP controller shall occur based on the value of TMSC at the time of a rising edge of TCKC.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock Frequency
TSMC 12nm18.87K125MHz
TSMC 28nm16.93K125MHz
TSMC 90nm18.94K125MHz
TSMC 130nm18.94K125MHz
TSMC 180nm21.55K125MHz
GF 180nm17.45K125MHz
SMIC 40nm17.38K125MHz
UMSC 55nm23.55K125MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e2822 LUT's125MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.