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AXI to UCIe Bridge IIP

AXI to UCIe Bridge IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech AXI to UCIe Bridge IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Enabling next-generation server, storage, and accelerator connectivity. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Throughput: Multi-lane architecture supporting maximum theoretical link speeds.

Low Latency: Optimized datapath for minimal latency, crucial for coherent interconnects like CXL and UCIe.

Virtualization Support: Hardware support for SR-IOV to enable efficient resource sharing in virtualized environments.

Reliability features: Advanced RAS (Reliability, Availability, and Serviceability) features for enterprise class stability.

FEATURES
  • Supports specification version 1.0, 1.1, 2.0 and 3.0
  • Supported Mode - Endpoint, Root Complex
  • Supported Package - Standard package, Advanced Package
  • Supported Protocol - AXI (Streaming protocol)
  • Supported Flit Format
    • Raw Format
    • 68B Flit Format
    • Standard 256B End Header Flit Format
    • Standard 256B Start Header Flit Format
    • Latency-Optimized 256B without Optional Bytes Flit Format
    • Latency-Optimized 256B with Optional Bytes Flit Format
  • Supports 4 GT/s, 8 GT/s, 12 GT/s, 16 GT/s, 24 GT/s, 32 GT/s, 48 GT/s and 64GT/s speeds with
    • 500 MHz, 1 GHz, 1.5 GHz, 2 GHz, 3 GHz, 4 GHz, 6GHz and 8 GHz UCIe clock frequency
  • Supports 800 MHZ speed for sideband data
  • Supports 16 Lanes, 32 Lanes and 64 Lanes
  • Supports Sideband messaging for link training and parameter exchange
  • Supports Sideband Mailbox Mechanism for read and write configuration
  • Supports Clock gating Mechanism
  • Supports all handshake mechanism
  • Supports Data Link Feature Exchange
  • Supports Link Power Management
  • Supports Multi Stack protocol
  • Supports all Vendor defined Sideband messages
  • Supports UCIe Retimers
  • Supports Flit Retry Mechanism
  • Supports Flits CRC
  • Compliant with the latest ARM AMBA AXI3 and ARM AMBA AXI4 Protocol Specification
  • Data Bus width configurable as 8,16,32,64,128,256,512 or 1024 bits wide
  • Separate address, data and response phases. Separate read and write channels
  • Support for burst-based transactions with only start address issued (Longer bursts up to 256 beats)
  • Supports Increment Burst type
  • Two versions of core available with one supporting multiple outstanding request with simultaneous access of write and read channel and the other that access either write or read at a time and not supporting outstanding request
  • Supports multiple outstanding request controlled by a Parameter
  • Support Positive edge clocking and no internal tri-states
  • Scan test ready
  • Fully synthesizable
  • Static synchronous design
  • Simple interface allows easy connection to microprocessor/ microcontroller devices
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules and provides the top level ports for the entire AXI to UCIe Bridge IP.

CSR: CSR module has all the registers. It decodes configuration data and assigns it to specific ports to drive the IP's functionality.

ATU: Address translation unit (ATU) module translates the UCIe specific address to csr address format.

PROTOCOL LAYER: The protocol layer performs APB-to-UCIe bridge to transfer sideband data using UCIe sideband packet formats and the AXI UCIe bridge manages high-speed data communication by converting AXI transactions into UCIe mainband flits and reconstructing them on reception.

D2D ADAPTER: The D2D Adapter module manages both sideband and mainband communication by packing, and unpacking sideband packets, while packaging protocol data into protected flits for reliable high-speed transfer between local and remote dies.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyLink Clock Frequency
TSMC 28nm140.6K100MHz8GHz
SMIC 40nm156.3K100MHz8GHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyLink Clock Frequency
AMD-xcvu9p-flga2104-2L-e23433 LUT's100MHz500MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.