Quad SPI Master IIP

• Compliant with features of Vendors such as Macronix, Winbond, Cypress and Micron SPI Specifications
• Full QUAD SPI Master Functionality
• Supporting Operating Modes: Single I/O, Dual I/O and QUAD I/O with Single and Double Transfer Rate (STR and DTR)
• Supports Frequency up to 166MHz
• Supporting Resets: Software Reset using Reset Command and Hardware Reset using Reset Pin
• Support 3-byte and 4-byte Addressing Capability to Enable Memory Access Beyond 128Mb
• Configuration Capability:
  • Volatile and Non-Volatile Configuration register settings to change the mode of the model, dummy cycle numbers for FAST Read Operation and 3-byte and 4-byte Addressing
• Supports a Wide Range of Device densities from 256Mb to 2Gb
• Supports Preamble bit to inputted the Selected Preamble Pattern to the Dummy cycle
• Configurable Transmit/Receive Data FIFO
• Direct Memory Access (DMA) support
• Supports of Fast Boot will have an ability to automatically execute read operation After Power on Reset or cycles without any Read command based on the Configuration of Fast Read Boot Register Values
• Supported Read Instructions:
  • READ
  • FAST READ
  • 2READ
  • DREAD
  • 4READ
  • QREAD
• Supported Write Instructions:
  • Page Program
  • Dual Page Program and
  • Quad Page Program
• Supports of Burst Length Command, user can to set 16-byte, 32-byte and 64-byte Wrap Bursts for Read Commands Deep power down mode Support (Does not accept other commands except Release and Exit from the Deep Power Down Command)
• Also supports Commands like Erase Commands, Security and Write Protection Commands with some other Additional Functionalities and Timing Commands
• AHB Slave Interface for Register Programming and PIO data Transfer
• AHB Master Interface for DMA Transfer
• Fully synthesizable
• Static synchronous design
• Scan test ready
• Simple host interfaces enable straightforward integration with microcontrollers and application processors

CORE: Core Module interconnects all the sub-modules in the SPI IP. Ports of core module are the top level ports for the SPI IP.

PRESCALER: Prescaler Module is used to divide the system clock based on the given prescaler value to drive the serial clock input for SPI.

FSM: FSM Module generates the SPI transcations on SPI Master based on commands from CSR block. This blocks implements all the features of SPI specifications.

ARB: ARB Module implements the arbiter to arbit between HCI and FSM access to CSR block.

HCI: HCI Module implements SPI Host controller FSM. The HCI FSM fetches the data from descriptor memory like SPI commands and transmit data bytes and it loads sampled read data bytes into descriptor memory.

XIP: XIP Module implements XIP/AIP mode operation with zero software overhead. XIP Module consists of functionality of both XIP and AIP mode. In XIP (Xecute In Place mode) executing the code directly from the serial flash memory .It will directly read from the Flash memory.In AIP (Access In Place) mode has both read and write operation will execute.It will write data into the flash device.XIP module is connected with soc Slave interface.

BOOT: Boot Module allows the host to read the data from the flash device after the power is on or after the hardware reset is done. It reads the data from the flash device without read command and address

CSR: CSR Module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

• Single Site license for regional development teams.
• Multi-Site license for global corporate deployments.
• Single Design license for specific project cost-efficiency.
• Unlimited Design license for high-volume product roadmaps.

• Complete Verilog/VHDL/SystemC Source Code.
• UVM-compliant verification environment with a comprehensive test suite.
• Production-ready synthesis, Lint, and CDC scripts.
• IP-XACT RDL generated address maps.
• Standard-compliant firmware and Linux/C driver packages.
• Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.