CORE: Core module interconnects all the sub-modules in the eSPI LPC Bridge IP. Ports of core module are the top level ports for the eSPI LPC Bridge IP.
FSM: FSM module receives the transactions from the eSPI Bus and process the serial data. This blocks implements all the features of eSPI specs. The information related to slave initiated is stored in Slave Tx FIFO before transaction starts and stores informations related to master initiated in Slave Rx FIFO. Transmission occurs independently any action of the Slave module.
VIRTUAL WIRE: Virtual wire module has the logic blocks to detect the changes in virtual wire input lines. When it detects the change in VW input line, it alerts the FSM to drive the alert signal and it also drives the VW changed data input FSM to drive it in a response phase of GET VW Command. Also it clears the change_detect signal based on the signal driven from FSM block on the reception of GET VW command. After clearing the change detect signal, if it detects the change in VW input again it repeats the above processes. This block works only when VW Channel enable configuration is enabled.
LPC-FSM: LPC - FSM module initiates LPC Host transactions on Host based ,Start opcodes from CSR block.
PRESCALER: Prescaler module is used to drive the Serial LPC clock from the system clock based on the programmed clock divider value.
SERIRO: This module controls to drive and sample the SERIRQ# signal to indicate LPC Interrupts to software.
BRIDGE: This Bridge FSM module helps to convert eSPI Slave command to LPC commands. Bridge module decodes the informations from FIFO by giving pop signal,those received informations are converted into LPC Frames and starts triggering LPC FSM by pending to LPC Host.
CSR: CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.
