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H.265 DECODER IIP

H.265 DECODER IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech High Efficiency Video Coding H.265 DECODER IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Delivering premium visual experiences for digital signage, broadcast, and consumer displays. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Quality Compression: Visually lossless compression algorithms optimized for minimal silicon area.

Real-Time Performance: Ultra-low latency processing suitable for live streaming and interactive applications.

Multi-Standard Support: Configurable to support various resolutions, frame rates, and color formats.

Power Efficient: Architecture optimized to minimize power consumption for portable multimedia devices.

FEATURES
  • High Efficiency Video Coding
  • Fully compatible with the ITU-T H.265 (V10) (07/2024) specification and ensures standard-adherent operation across all supported configurations.
  • Supports all Profiles and levels upto 7.2.
  • Dynamically Supports multiple slices and tiles for better error resilience.
  • Supports configurable input bitstream processing of 32,64 and 128 bits per clock.
  • Supports configurable output pixel processing of 4,8 and 16 pixels per clock.
  • Supports Variable Bit Rate and Constant Bit Rate.
  • Supports maximum resolution upto 16k@120Hz.
  • Compatible with the video formats which are mentioned in V10.
    • YCbCr 4:4:4 (24,30,36,42,48 Bits Per Pixel).
    • YCbCr 4:2:2 (16,20,24 Bits Per Pixel).
    • YCbCr 4:2:0 (12,15,18 Bits Per Pixel).
    • Y(Monochrome) (8,10,12 Bits Per Pixel).
  • Supports Coding Tree Unit (CTU) with size of 64x64.
  • Supports Coding Unit (CU) with sizes of 8x8,16x16,32x32,64x64.
  • Supports Prediction Unit (PU) with sizes of 4x4,8x8,16x16,32x32,64x64.
  • Supports Transform Unit (TU) with sizes of 4x4,8x8,16x16,32x32.
  • Supports both intra and inter prediction process.
  • Supports SATD/SAD/SSE for Rate Distortion Optimization(RDO).
  • Supports Skip/Merge mode in inter prediction.
  • Supports Intra CTU in Inter frame.
  • Supports CABAC entropy process.
  • Supports Block skipping (PCM) for lower bitrate.
  • Supports Palette Mode prediction process.
  • Supports Cross component prediction process (For 4:4:4 color format).
  • Supports De-blocking and Sample Adaptive Offset (SAO) filter for better quality.
  • Supports Picture cropping for image sizes that are not a multiple of 64 pixels.
  • Supports Chroma Quantization Parameter offset for increased compression.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller.
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the H.265 Decoder IIP. Ports of core module are the top level ports for the H.265 Decoder IIP.

NAL DECODER: NAL Decoding module is used to convert the compressed video data (NAL units) into video frames.

CABAC: CABAC module used to perform the entropy decoding and it decodes the CABAC-encoded syntax elements such as prediction modes,motion data into quantized coefficients.

DEQUANTIZATION: Dequantization module is used to restores the scale of quantized coefficients by applying inverse quantization method using the quantization parameter.

INVERSE TRANSFORM: Inverse Transform module converts dequantized transform coefficients back to reconstruct the prediction residual.

PREDICTION: Prediction module performs intra prediction for luma and chroma blocks. It computes prediction samples for all supported prediction modes.

RECONSTRUCTION: Reconstruction module rebuilds the frame by adding the residual data from inverse transformation and predicted data from prediction block.

DEBLOCKING & SAO FILTERS : Deblocking filter smoothens the image edges and SAO filter enhances the video quality after deblocking.

COLOUR SPACE CONVERSION: Colour space conversion module is used to convert the frame from one colour format (YCbCr) into another (RGB).

CSR: The CSR module contains all control and status registers. These registers used to control the RTL functionality and to monitor its status.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyVideo Clock Frequency
TSMC 28nm1000K200MHz148.5MHz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyVideo Clock Frequency
AMD-xcvu9p-flga2104-2L-e166666 LUT's150MHz148.5MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.