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USB2.x OTG IIP

Universal Serial Bus 2.x On-The-Go IIP

USB2.x OTG IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech USB2.x OTG IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Perfect for consumer electronics, peripherals, and embedded IoT devices. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Certified Interoperability: Extensive testing against standard USB hosts and devices to guarantee plug-and-play compatibility.

Highly Configurable: Flexible endpoint configuration and FIFO sizing to optimize area vs. performance trade-offs.

Low Power Modes: Aggressive power management supporting Suspend/Resume and remote wakeup capabilities.

Legacy Support: Backward compatibility ensuring seamless operation with older USB revisions.

FEATURES
  • Compliant with USB OTG EH 2 Revision 1.1a and all associated ECN
  • Compliant with USB OTG EH 3 Revision 1.0 compliant and all associated ECN’s.
  • Compliant with USB 2.0 specification.
  • Compliant to EHCI Specification Rev 1.0
  • Compliant to xHCI Specification Rev 1.2
  • Supports UTMI and ULPI transceivers.
  • Supports HNP/SRP/ADP features
  • Supports configurable USB Speeds – HS/FS/LS
  • All USB 1.1 transfer types are supported.
  • Operates at High-speed (480 Mbps), Full-speed (12Mbps) and Low-speed (1.5 Mbps).
  • Supports Attach/Detach, reset signaling and suspend/resume.
  • Software configurable Supports UTMI Parallel and serial mode.
  • USB2 PHY Interface: 8/16 bits UTMI plus level 3
  • Enumeration of low-speed, full-speed, and high-speed devices.
  • Supports Interrupt/Bulk/Isochronous/Control Transfers.
  • Supports High Bandwidth Interrupt and Isochronous endpoints.
  • CRC5 generation and checking for Tokens.
  • CRC16 checking and generation for HS/FS/LS data packets.
  • Control transfers supported by Endpoint 0
  • Supports configurable internal buffers and Protocol Layer Error Handling.
  • Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
  • Supports maximum payload size for each endpoint.
  • Supports USB Suspend state and supports remote wakeup devices.
  • Supports all HS/FS USB Link Power Management States – L1, L2.
  • Implements all the EHCI and xHCI compliant registers.
  • Proprietary DMA engine for initiating/completing USB transactions limiting software overhead. Can be used with Host mode operation.
  • Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.
  • Supports preamble for LS transfers while operating in Embedded Host Mode.
  • Configurable number of Downstream ports for Embedded Host Applications. Supports multiple devices connected under HS/FS hub for Embedded Host Applications.
  • Support USB 2.0 Test mode. Supports USB Suspend state and supports remote wakeup devices.
  • Support for clock gating and multi-power-well support.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple host interfaces enable straightforward integration with microcontrollers and application processors Available as Additional Feature at extra cost
  • ISO26262 Functional safety(ASIL B/D)
    • ISO26262 Safety Manual (SAM) Document
    • ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
  • Memories with ECC
  • Internal DMA
  • Basic Firmware – Linux Driver
  • Customer SoC I/F
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules within the USB2 OTG IP.It exposes the top level interfaces of the IP and supports OTG,Host and Device mode of operation,enabling seamless integration into system design.

OTG FSM: FSM Module is used to determine the OTG role as either A device or a B device. The FSM will covers OTG protocols such as HNP,SRP and ADP

OTG CSR: OTG CSR module has all the Control and Status registers. Implements Interrupts for both host and device mode and includes all OTG timers.

USB TRANSACTOR: USB Transactor module implements the logic for transmitting and receiving High, Full and Low speed packets and manages various USB bus conditions.

TRANSACTION SCHEDULER: Transaction Scheduler module schedule the transfer based on the endpoint type and pushes the device and endpoint address in periodic and non-periodic scheduling pipe and managing the endpoint and device contexts and Maintaining the dequeue pointer and data buffer pointer for each and every endpoint.

COMMAND PROCESSOR: Command Processor module fetches the command TRB from command ring and decode and process it and update the device contexts based on the command operation and generates the event trb for the command and sends it to the event ring controller block.

EVENT RING CONTROLLER: Event Ring Controller module manages event ring FULL and empty condition checking and generating event ring full event and interrupt based on the event ring empty condition, interrupt moderation, interrupt interval counter.

HOST CSR: HOST CSR module has all the registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

PROTOCOL LAYER: Protocol Layer module takes care of packet disassembler and packet assembler and data processing in protocol engine.

CONTROL: Control module will take care of all standard device requests with respect to endpoint zero.

ROM1: Rom will store the descriptor details of endpoint zero from which the data can be retrieved.

ENDPOINT PROCESSOR: Endpoint Processor will organize the endpoint config details with respect to transfer type, config type, and config size. It then mediates the data read and write and other signals from fifo.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesSystem Clock FrequencyUTMI Clock FrequencyReference Clock Frequency
TSMC 28nm261K200Mhz60Mhz25Mhz
UMSC 55nm502K200Mhz60Mhz25Mhz
SMIC 40nm285K200Mhz60Mhz25Mhz

FPGA Device and FamilyLogic ResourcesSystem Clock FrequencyUTMI Clock FrequencyReference Clock Frequency
AMD Virtex-7 FPGA(xc7vx485tffg1761-2)43500 LUT's200Mhz60Mhz25Mhz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.