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Ethercat Slave IIP

Ethercat Slave IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech Ethercat Slave IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility andease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES
  • Supports ETG.1000 S(R) V1.0.4 specification.
  • 8 SYNC Manager
  • 8 FMMU's
  • 8kB Process Data RAM
  • 64 Bit Distributed Clocks
  • Can connect with SPI/I2C/UART interfaces based on application
  • MAC is Compliant with IEEE Standard 802.3.2022 specification
  • Supports EtherCAT frame inside an Ethernet frame
  • Supports all types of EtherCAT data frames
  • Supports the standard TCP-IP and UDP-IP protocols
  • Supports Full duplex transmission
  • Supports Sync Manager and Mailbox
  • Supports Field Bus Memory Management Unit
  • Supports Error Detection using Ethernet’s Frame Check Sequence
  • Supports MII and RMII Interfaces for Ethernet PHY
  • Supports conformance tests as per ETG.7000.2 V1.0.6 specification
  • Provides detailed statistics as per the specification
  • Supports MDIO (Clause 22 and Clause 45) Interface
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the EtherCAT Slave IP. Ports of core module are the top level ports for the EtherCAT Slave IP.

FMMU: This block maps the logical addresses from the master to local physical memory of the slave.

ADDRESS DECODER: For this module, the output frame fifo data from the fifo is given as input, here the FSM samples the Protocol data unit through the Command,Index,Position address and offset address states.

ADDRESS MAPPING: In this module based on the PDU's Position address and offset address, the data will be read and write to the register or memory.

SPI Interface: In this module based on the cmd opcode the output from the Address mapping module is driven as input to this module.Based on the wr_cmd and rd_cmd the data will be written or read.The output from this module is considered as FMMU output.

SYNC MANAGER: Sync manager block enable consistent and secure data exchange between the EtherCAT master and the local application.

FRAME DECODER: This module decodes the ethernet frame based on the Preamble,SFD detections and its MII signals which is enable,err,data. It also decodes the ethertype and based on this it decodes the frame fields for all ethertype[EtherCAT, UDP, VLAN IPV4]. It also set the IRQ registers for the frames errors.

RESPONSE GENERATION: In this module, the frame will be send with SOP. The output from the edit frame is concatenate with response valid and error signal then the concatenated data will be given as input to the fifo.

PROCESSING UNIT: This block is used to handles the data link layer frames, responsible for the actual data manipulation deciding what to read, and how to synchronize with the the local application.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION
ASIC TechnologyLogic ResourcesClock FrequencyMAC Clock FrequencyMAC Clock Frequency
TSMC 28nm332.23K167.66MHz25MHz50MHz
UMSC 55nm437.42K167.66MHz25MHz50MHz
SMIC 40nm382.59K167.66MHz25MHz50MHz

FPGA Device and FamilyLogic ResourcesClock Frequency
AMD-xcvu9p-flga2104-2L-e55333 LUT's167.66MHz

LICENSING OPTIONS
  • Single Site license for regional development teams.
  • Multi-Site license for global corporate deployments.
  • Single Design license for specific project cost-efficiency.
  • Unlimited Design license for high-volume product roadmaps.
DELIVERABLES
  • Complete Verilog/VHDL/SystemC Source Code.
  • UVM-compliant verification environment with a comprehensive test suite.
  • Production-ready synthesis, Lint, and CDC scripts.
  • IP-XACT RDL generated address maps.
  • Standard-compliant firmware and Linux/C driver packages.
  • Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.