ASA IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ASA IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Professional grade IP core for embedded system design. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Production Proven: Validated in silicon and FPGA across diverse applications.

Cost Efficient: Competitive licensing models designed to lower the barrier to entry for custom silicon.

Expert Support: Direct access to senior design engineers for rapid integration assistance.

Flexible Deliverables: Available as synthesizable source code or optimized netlists.

FEATURES

Supports Automotive SerDes specification version 1.01, 1.1, 2.0 and 2.1.
Supports PCS layer and Data link layer features.
Supports Application Stream Encapsulation (ASE) and Application Stream Decapsulation (ASD).
Supports OAM (Operation, Administration, Management).
Supports comprehensive security framework including an efficient key exchange mechanism and link layer security.
Supports FOFA (Forwarding Fabric) with normal mode and enumerate mode.
Supports half-duplex physical layer.
Supports asymmetric payload data rates split between Downstream (high rate) and Upstream (low rate) direction and separated by an Inter Burst Gap (IBG).
Supports multiplexing and demultiplexing of application and internal data streams in data link layer.
Supports optionally for the stream types of ASEP like Video data, I2C, Ethernet frame, SPI, GPIO, embedded display port (eDP), I2S, Mipi CSI-2 , ASA Control Channel(ACC) and test ASEP.
Supports time-division access mechanism.
Supports following startup phases

Startup Phase 1G
Startup Phase SGA
Startup Phase SGB
Startup Phase SGC

Supports multiple speed grades ranging from 2Gbps up to 16Gbps.
Supports downlink data rates up to 16 Gbps.
Supports uplink data rates greater than 100 Mbps.
Supports PCS scrambling and descrambling.
Supports RS-FEC encoding and decoding.
Supports PTB (Precision Time Base).
Supports PAM2 mapping and PAM4 gray encoding process.
Supports light sleep feature that enables a duty cycling of the physical layer between active and disabled state.
Supports automatic startup of link partners into normal mode as well as startup into test mode.
Supports Security Encryption and Decryption (AES_GCM and AES_GMAC).
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple interface allows easy connection to microprocessor/microcontroller.

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ASA IP. Ports of core module are the top level ports for the ASA IP.

TX: This module implements ASA transmit path. It contains the instances of DLL, LAS and PCS. This module is instantiated in core and responsible for data transmission.

RX: This module implements ASA receive path. It contains the instances of DLL, LAS and PCS. This module is instantiated in core and responsible for data reception.

TRAN_FSM: This module implements ASA transceiver state machine. It indicates the starting and transitions of startup and OAM and normal modes. It controls the following fsms such as startup, test mode, OAM config, normal mode, light sleep and deep sleep.

CSR: CSR module has all the Control and status registers. The Control and Status Register (CSR) Module maintains all the configuration and monitoring registers used by the ASA IP.This block contains interrupt enable and status registers.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency	DLL Clock Frequency	PMA Tx Clock Frequency	PMA Rx Clock Frequency
TSMC 28nm	135k	62.5MHz	500MHz	500MHz	500MHz
SMIC 40nm	163k	62.5MHz	500MHz	500MHz	500MHz
UMSC 55nm	296k	62.5MHz	500MHz	500MHz	500MHz

FPGA Device and Family	Logic Resources	System Clock Frequency	DLL Clock Frequency	PMA Tx Clock Frequency	PMA Rx Clock Frequency
AMD-xcvu9p-flga2104-2L-e	22500 LUT's	62.5MHz	125MHz	125MHz	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.