ETHERNET 2.5G MAC IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 2.5G MAC IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Compliant with IEEE Standard 802.3-2022 specification clause 46
Supports full duplex mode of operation
Supports standard 2.5Gbps Ethernet link layer data
Supports XGMII interface operating at 78.125MHz
Supports Programmable Inter Packet Gap and Preamble length
Supports MDIO Clause 45 Interface
Supports start control character alignment
Provides detailed statistics as per specification
Supports Jumbo Frame
Supports Loopback functionality
Supports transmit and receive FIFO interface
Supports FCS(CRC) transmission and reception
Supports Pause frame-based flow control
Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
Supports Wake-on-LAN
Supports AXI stream Interface for System Interface
In house UNH compliance tested
Optional support for TCP/IP
Optional support for IEEE Standard 1588-2008 PTP
Optional support for DMA support for both transmit and receive side
Optional support for the following HiGig features

HiGig
HiGig+
HiGig2
HiGigLite
2.5G HiGig

Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the ETHERNET 2.5G MAC IP. Ports of core module are the top level ports for the ETHERNET 2.5G MAC IP.

TX CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX ASYNC FIFO: TX ASYNC FIFO module stores Transmitted data and process the data with the different read and write clock domain.

TX FSM: The TX FSM module receives the data from MAC client and maps them to the MAC XGMII Interface by encapsulating the Ethernet packet and frame headers.

FLOW CTRL: Initiating the Transmission of pause frame-based on the Receive FIFO's threshold or External requests.

PAUSE TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

LINK FAULT FSM: LINK FAULT FSM module detects the fault status from the received data and indicates status to the TX.

RX FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

RX ASYNC FIFO: RX ASYNC FIFO module stores Received data and process the data with the different read and write clock domain.

RX CTRL : Receive Control block processes the data from MAC XGMII interface and push the data into RX ASYNC FIFO.

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames.

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	System Clock Frequency	MAC Clock Frequency
TSMC 28nm	36.95K	78.125MHz	78.125MHz	78.125MHz
UMSC 55nm	73.46K	78.125MHz	78.125MHz	78.125MHz
SMIC 40nm	54.12K	78.125MHz	78.125MHz	78.125MHz

FPGA Device and Family	Logic Resources	Clock Frequency	System Clock Frequency	MAC Clock Frequency
Altera Stratix 10,6158 LUT's	78.125MHz	78.125MHz	78.125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.