HDMI Source v2.0 IIP

High Definition Multimedia Interface Source v1.4/2.0 IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech HDMI Source v2.0 IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Delivering premium visual experiences for digital signage, broadcast, and consumer displays. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

High Quality Compression: Visually lossless compression algorithms optimized for minimal silicon area.

Real-Time Performance: Ultra-low latency processing suitable for live streaming and interactive applications.

Multi-Standard Support: Configurable to support various resolutions, frame rates, and color formats.

Power Efficient: Architecture optimized to minimize power consumption for portable multimedia devices.

FEATURES

HDMI Source v2.0
Fully compliant with HDMIv2.0b specification and ensures standard-adherent operation across all supported configurations.
Backward compatible with HDMIv1.4b.
Supports TMDS Character link rates from 340 Mcsc to 600 Mcsc.
Supports configurable output pixel processing of 1,2,4 and 8 pixels per clock.
Supports programmable parallel interface widths of 10bits, 20bits ,40bits and 80bits.
Supports maximum resolution upto 4k@60hz.
Compatible with the video formats which are mentioned in HDMIv2.0b,

RGB 4:4:4 (24,30,36,48 Bits Per Pixel)
YCbCr 4:4:4 (24,30,36,48 Bits Per Pixel)
YCbCr 4:2:2 (24 Bits Per Pixel)
YCbCr 4:2:0 (24,30,36,48 Bits Per Pixel)

Compatible upto 32 audio channels.
Compatible with audio sample rates from 32 KHz to 1.536 MHz.
Compatible with standard and compressed audio formats including,

Audio Sample (L-PCM, IEC 60958 and IEC 61937 compressed formats)
ACP packet and DST audio packet
High Bitrate (HBR) Audio Stream Packet (IEC 61937)
Audio InfoFrame and Audio Metadata Packet
3D Audio Sample Packet (L-PCM format only) and One Bit 3D Audio Sample Packet
Multi-Stream Audio Sample Packet and One Bit Multi-Stream Audio Sample Packet
Dynamic Range and Mastering InfoFrame

Supports all secondary video data packet formats including,

Null packet
General Control packet
ISRC packet
Gamut Metadata Packet
Vendor-Specific InfoFrame
AVI InfoFrame
Audio Clock Regeneration

Performs 8b/10b,2b/10b,TERC4 encoding and data scrambling.
Supports Error Correction Codes (ECC) to perform error correction in Dataisland packet.
Compatible with HDCP 1.4 (for HDMI v1.4b) and HDCP 2.2 (for HDMI v2.0b) Content protection.
Compatible with Audio Return Channel (ARC).
Compatible with Display Data Channel (DDC).
Compatible with CEC 1.4b (for HDMI v1.4b) and CEC 2.0 (for HDMI v2.0b).
Compatible with legacy DVI and Dual-Link DVI Standards.
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple host interfaces enable straightforward integration with microcontrollers and application processors.

FUNCTIONAL DESCRIPTION

CSR: Contains all configuration registers used to monitor status and control the RTL functionality.

DATA ISLAND PACKER: Assembles and packs secondary data packets(including audio, Infoframes, control and metadata packets) into a specification-complaint format.

VIDEO PACKER: Packs the incoming pixel data based on the configure color space(type) and color depth.

PREAMBLE PACKER: Inserts preamble sequences to indicate the upcoming period type (Video Data, Data Island, or control) and ensure proper link synchronization with the sink device.

TMDS LOGICAL PHY: Performs period-based encoding (for Video, Data Island and Control periods) and handles data scrambling to ensure reliable TMDS transmission.

GEARBOX: Takes the encoded data and converts it into a 10bit, 20bit, 40 bit or 80 bit parallel output data stream on the width of the connected Serdes.

HPD EVENT PROCESSING: Monitors HDMI sink Hot-Plug Detect(HPD) events to dynamically trigger link initialization and EDID reads.

CEC: Enables single-wire control communication for device discovery, command exchange and overall system interoperability.

I2C MASTER: Performs sink communication for EDID and SCDC access, enabling capability detection, link configuration and status monitoring.

eARC RX: Receives, validates and forwards high-bitrate audio from the sink using a dedicated control and data channel.

I2S/SPDIF: Acts as the dedicated audio interface bridging the SoC's audio subsystem and HDMI core.

HDCP: Provides cryptographic authentication, key exchange, and encryption, ensuring the secure transmission of protected audio and video content between the HDMI Source and Sink Devices.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	System Clock Frequency	Secondary Clock Frequency	Video Clock Frequency	TMDS Clock Frequency	Serdes Clock Frequency
TSMC 28nm	118.98K	100MHz	100MHz	37.125MHz	74.25MHz	74.25MHz
SMIC 40nm	126.20K	100MHz	100MHz	37.125MHz	74.25MHz	74.25MHz
UMC 55nm	227.58K	100MHz	100MHz	37.125MHz	74.25MHz	74.25MHz

FPGA Device and Family	Logic Resources	System Clock Frequency	Secondary Clock Frequency	Video Clock Frequency	TMDS Clock Frequency	Serdes Clock Frequency
AMD-xcvu9p-flga2104-2L-e	45516 LUT's	100MHz	100MHz	37.125MHz	74.25MHz	74.25MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.