ETHERNET 800G MAC IIP

Overview

COMPETITIVE ADVANTAGE

The SivaKali Tech ETHERNET 800G MAC IIP is a highly reliable, silicon-proven IP core designed for high-performance system integration. Engineered to meet strict industry compliance standards, this core offers exceptional flexibility and ease of integration into both ASIC and FPGA designs. Designed for data center, enterprise networking, and industrial automation environments. Validated on leading FPGA platforms and foundry nodes, it provides a low-risk, time-to-market advantage for developers.

COMPETITIVE ADVANTAGE

Low Latency Architecture: Engineered for real-time applications with deterministic latency, ideal for TSN (Time Sensitive Networking).

Scalable Performance: Seamless migration paths from 10M to 800G, supporting a wide range of networking requirements.

Robust Compliance: Fully compliant with IEEE 802.3 standards, ensuring interoperability with standard network equipment.

Integrated Offload: Advanced TCP/UDP offload engines (TOE) to reduce host processor overhead.

FEATURES

Compliant with IEEE Standard 802.3-2022 specification
Supports full duplex mode of operation
Supports Standard 800Gbps Ethernet link layer data
Supports 1024 bit CDMII interface
Supports Programmable Inter Packet Gap(IPG) and Preamble length
Supports MDIO (Clause 22 and Clause 45) Interface
Supports start control character alignment
Provides detailed statistics as per the specification
Supports Jumbo Frame
Supports Loopback functionality
Supports transmit and receive FIFO interface
Supports FCS(CRC) transmission and reception
Supports Pause frame-based flow control
Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
Optional Wake-on-LAN support
In house UNH compliance tested
Optional support for TCP/IP offload
Optional support for IEEE Standard 1588-2008 PTP
Optional support for DMA on both transmit and receive side
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple host interfaces enable straightforward integration with microcontrollers and application processors

FUNCTIONAL DESCRIPTION

CORE: Core module interconnects all the sub-modules in the Ethernet 800G MAC IIP . Ports of core module are the top level ports for the Ethernet 800G MAC IIP.

TX-CTRL: Transmit Control block processes the data from system interface/AXI-interfaces and push the data into Transmit FIFO.

TX_FIFO : TX ASYNC FIFO module stores TX data and processes it with the different read and write clock domain.

Transmit MAC TX-FSM: The transmit FSM receives the data from MAC client and maps them to the MAC 800G Interface by encapsulating the Ethernet packet and frame headers

RX-CTRL: RX Control block processes the data from MAC 800G interface and push the data into Rx ASYNC FIFO.

RX_FIFO : RX ASYNC FIFO module stores Rx data and process the data with the different read and write clock domain.

Receive MAC RX-FSM: The Receive FSM receives the data from underlying physical layer and sends them to MAC client by decapsulating the Ethernet Packet headers.

FLOW CTRL: Initiating the Transmission of pause frame-based on the Receive FIFO's threshold or External requests.

PAUSE_TIMER: Implements the Pause timer logic based on the Pause Quanta Value.

LINK FAULT FSM: The Link Fault FSM module indicates the RX and TX link status, the local fault signal indicates by PHY layer.when the local fault signal reached the RS layer, the RS continuously generate the remote fault signal on CDMII TXD and TXC output signal

MDIO: The MDIO Master serial interface is used to control the PHY registers with read and write frames

CSR: CSR Module has all the configurable registers. The contents of the registers are decoded and assigned to its respective output ports based on its functionality.

ASIC AND FPGA IMPLEMENTATION

ASIC Technology	Logic Resources	Clock Frequency	System Clock Frequency	MAC Clock Frequency
TSMC 28nm	196.36K	78.125MHz	78.125MHz	3.125GHz
UMSC 55nm	227.45K	78.125MHz	78.125MHz	3.125GHz
SMIC 40nm	208.36K	78.125MHz	78.125MHz	3.125GHz

FPGA Device and Family	Logic Resources	Clock Frequency	System Clock Frequency	MAC Clock Frequency
AMD-xcvu9p-flga2104-2L-e	32726 LUT's	78.125MHz	78.125MHz	125MHz

LICENSING OPTIONS

Single Site license for regional development teams.
Multi-Site license for global corporate deployments.
Single Design license for specific project cost-efficiency.
Unlimited Design license for high-volume product roadmaps.

DELIVERABLES

Complete Verilog/VHDL/SystemC Source Code.
UVM-compliant verification environment with a comprehensive test suite.
Production-ready synthesis, Lint, and CDC scripts.
IP-XACT RDL generated address maps.
Standard-compliant firmware and Linux/C driver packages.
Detailed documentation: User Guides, Release Notes, and ISO 26262 Safety Manual (SAM)/FMEDA.